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Challenges and opportunities in many-core computing

PROCEEDINGS OF THE IEEE 2008年第5期96卷 808-815页

作者： Manferdelli, John L. Govindaraju, Naga K. Crall, Chris Microsoft Corp Redmond WA 98052 USA

In this paper, we present some of the challenges and opportunities in software development based on the current hardware trends and the impact of massive parallelism on both the software and hardware industry. We indicate some of the approaches that can enable software development to effectively exploit the many-core architectures. Some of these include encapsulating domain-specific knowledge in reusable components, such as libraries, integrating concurrency with languages, and supporting explicit declarations to help compilers and operating system schedulers. Tighter interaction between software and underlying hardware is required to build scalable and portable applications with predictable performance and higher power-efficiency. overall, many-core computing provides us opportunities to enable new application scenarios that support enhanced functionality and a richer experience for the user on commodity hardware.

关键词： compilers many-core computing operating systems parallel applications

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The hardware accelerator debate: A financial risk case study using many-core computing

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COMPUTERS & ELECTRICAL ENGINEERING 2015年 46卷 157-175页

作者： Varghese, Blesson Univ St Andrews Sch Comp Sci St Andrews KY16 9AJ Fife Scotland

The risk of reinsurance portfolios covering globally occurring natural catastrophes, such as earthquakes and hurricanes, is quantified by employing simulations. These simulations are computationally intensive and require large amounts of data to be processed. The use of many-core hardware accelerators, such as the Intel Xeon Phi and the NVIDIA Graphics Processing Unit (GPU), are desirable for achieving high-performance risk analytics. In this paper, we set out to investigate how accelerators can be employed in risk analytics, focusing on developing parallel algorithms for Aggregate Risk Analysis, a simulation which computes the Probable Maximum Loss of a portfolio taking both primary and secondary uncertainties into account. The key result is that both hardware accelerators are useful in different contexts;without taking data transfer times into account the Phi had lowest execution times when used independently and the GPU along with a host in a hybrid platform yielded best performance. (C) 2015 Elsevier Ltd. All rights reserved.

关键词： Hardware accelerators many-core computing Secondary uncertainty Financial risk Catastrophic risk Risk analysis

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computing probable maximum loss in catastrophe reinsurance portfolios on multi-core and many-core architectures

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2016年第3期28卷 836-847页

作者： Burke, Neil Rau-Chaplin, Andrew Varghese, Blesson Dalhousie Univ Fac Comp Sci Halifax NS Canada Univ St Andrews Sch Comp Sci North Haugh St Andrews Fife Scotland

In the reinsurance market, the risks natural catastrophes pose to portfolios of properties must be quantified, so that they can be priced, and insurance offered. The analysis of such risks at a portfolio level requires a simulation of up to 800000 trials with an average of 1000 catastrophic events per trial. This is sufficient to capture risk for a global multi-peril reinsurance portfolio covering a range of perils including earthquake, hurricane, tornado, hail, severe thunderstorm, wind storm, storm surge and riverine flooding, and wildfire. Such simulations are both computation and data intensive, making the application of high-performance computing techniques desirable. In this paper, we explore the design and implementation of portfolio risk analysis on both multi-core and many-core computing platforms. Given a portfolio of property catastrophe insurance treaties, key risk measures, such as probable maximum loss, are computed by taking both primary and secondary uncertainties into account. Primary uncertainty is associated with whether or not an event occurs in a simulated year, while secondary uncertainty captures the uncertainty in the level of loss due to the use of simplified physical models and limitations in the available data. A combination of fast lookup structures, multi-threading and careful hand tuning of numerical operations is required to achieve good performance. Experimental results are reported for multi-core processors and systems using NVIDIA graphics processing unit and Intel Phi many-core accelerators. Copyright (c) 2015 John Wiley & Sons, Ltd.

关键词： risk analysis secondary uncertainty many-core computing hardware accelerators

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Larrabee: A many-core x86 architecture for visual computing

Larrabee: A many-core x86 architecture for visual computing

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ACM SIGGRAPH Conference 2008

作者： Seiler, Larry Carmean, Doug Sprangle, Eric Forsyth, Tom Abrash, Michael Dubey, Pradeep Junkins, Stephen Lake, Adam Sugerman, Jeremy Cavin, Robert Espasa, Roger Grochowski, Ed Juan, Toni Hanrahan, Pat Intel Corp Santa Clara CA 95051 USA Stanford Univ Stanford CA 94305 USA

This paper presents a many-core visual computing architecture code named Larrabee, a new software rendering pipeline, a many-core programming model, and performance analysis for several applications. Larrabee uses multiple in-order x86 CPU cores that are augmented by a wide Vector processor unit, as well as some fixed function logic blocks. This provides dramatically higher performance per watt and per unit of area than out-of-order CPUs on highly parallel workloads. It also greatly increases the flexibility and programmability of the architecture as compared to standard GPUs. A coherent on-die 2(nd) level cache allows efficient inter-processor communication and high-bandwidth local data access by CPU cores. Task scheduling is performed entirely with software in Larrabee, rather than in fixed function logic. The customizable software graphics rendering pipeline for this architecture uses binning in order to reduce required memory bandwidth, minimize lock contention, and increase opportunities for parallelism relative to standard GPUs. The Larrabee native programming model supports a variety of highly parallel applications that use irregular data structures. Performance analysis on those applications demonstrates Larrabee's potential for a broad range of parallel computation.

关键词： graphics architecture many-core computing real-time graphics software rendering throughput computing visual computing parallel processing SIMD GPGPU

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Larrabee: A many-core x86 architecture for visual computing

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ACM TRANSACTIONS ON GRAPHICS 2008年第3期27卷

关键词： graphics architecture many-core computing real-time graphics software rendering throughput computing visual computing parallel processing SIMD GPGPU

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Larrabee: a many-core x86 architecture for visual computing 08

Larrabee: a many-core x86 architecture for visual computing

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ACM SIGGRAPH 2008 papers

作者： Larry Seiler Doug Carmean Eric Sprangle Tom Forsyth Michael Abrash Pradeep Dubey Stephen Junkins Adam Lake Jeremy Sugerman Robert Cavin Roger Espasa Ed Grochowski Toni Juan Pat Hanrahan Intel® Corporation RAD Game Tools Stanford University

ISBN: (纸本)9781450301121

This paper presents a many-core visual computing architecture code named Larrabee, a new software rendering pipeline, a manycore programming model, and performance analysis for several applications. Larrabee uses multiple in-order x86 CPU cores that are augmented by a wide vector processor unit, as well as some fixed function logic blocks. This provides dramatically higher performance per watt and per unit of area than out-of-order CPUs on highly parallel workloads. It also greatly increases the flexibility and programmability of the architecture as compared to standard GPUs. A coherent on-die 2nd level cache allows efficient inter-processor communication and high-bandwidth local data access by CPU cores. Task scheduling is performed entirely with software in Larrabee, rather than in fixed function logic. The customizable software graphics rendering pipeline for this architecture uses binning in order to reduce required memory bandwidth, minimize lock contention, and increase opportunities for parallelism relative to standard GPUs. The Larrabee native programming model supports a variety of highly parallel applications that use irregular data structures. Performance analysis on those applications demonstrates Larrabee's potential for a broad range of parallel computation.

关键词： parallel processing visual computing graphics architecture many-core computing throughput computing SIMD software rendering GPGPU realtime graphics

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Larrabee: a many-core Intel® architecture for visual computing 09

Larrabee: a many-core Intel® architecture for visual comput...

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Proceedings of the 6th ACM conference on computing frontiers

作者： Ronny Ronny Ronen Intel Corporation Haifa Israel

ISBN: (纸本)9781605584133

The ample supply of transistors provided by advancements in process technology, combined with the increased difficultly to exploit single thread performance, moved the industry to populate several cores on a single die. This talk presents Larrabee -- the next bold step in this *** is a many-core visual computing architecture. Larrabee uses multiple in-order X86 CPU cores that are augmented by a wide vector processor unit, as well as some fixed function logic blocks. This provides dramatically higher performance per watt and per unit of area than out-of-order CPUs on highly parallel workloads. It also greatly increases the flexibility and programmability of the architecture as compared to standard GPUs. A coherent on-die 2nd level cache allows efficient inter-processor communication and high-bandwidth local data access by CPU cores. The customizable software graphics rendering pipeline for this architecture uses binning in order to reduce required memory bandwidth, and increase opportunities for parallelism relative to standard GPUs. The Larrabee native programming model supports a variety of highly parallel applications that use irregular data structures.

关键词： software rendering many-core computing graphics architecture parrallel processing processor arechitecture

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High-performance simulations of turbulent boundary layer flow using Intel Xeon Phi many-core processors

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JOURNAL OF SUPERcomputing 2021年第9期77卷 9597-9614页

作者： Kang, Ji-Hoon Hwang, Jinyul Sung, Hyung Jin Ryu, Hoon Korea Inst Sci & Technol Informat Div Natl Supercomp Daejeon 34141 South Korea Korea Adv Inst Sci & Technol Dept Mech Engn Daejeon 34141 South Korea Pusan Natl Univ Sch Mech Engn Busan 46241 South Korea

Direct numerical simulations (DNS) of turbulent flows have increasing importance because they not only provide fundamental understanding of turbulent flows but also complement and extend experimental results. DNS of high Reynolds numbers, however, require huge computing cost so high-performance computing has been strongly pursued. In this study, we examine the feasibility of cost-efficient DNS on Intel Xeon Phi many-core processors that are currently adopted by 10% of the 100 largest supercomputers in the world as listed in the Top500 site. For this purpose, we port and optimize our in-house turbulent flow solver named as DNS-TBL (direct numerical simulation-turbulent boundary layer) on Xeon Phi Knights Landing (KNL) many-core processors and conduct benchmark tests on KNL and conventional multicore processors. The key architectural features of KNL processors and strategies to exploit them for performance enhancement are discussed. The optimized code is validated by conducting numerical simulations of zero-pressure gradient turbulent boundary layers at high Reynolds numbers and by comparing simulated turbulent statistics to those reported in previous studies. With the details of optimization strategies and validation processes, this work can serve as a practical guideline for acceleration of large-scale and precise DNS with many-core computing.

关键词： Computational fluid dynamics Direct numerical simulations of turbulent flows many-core computing Xeon Phi knights landing processors

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Tpetra, and the use of generic programming in scientific computing

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SCIENTIFIC PROGRAMMING 2012年第2期20卷 115-128页

作者： Baker, C. G. Heroux, M. A. Oak Ridge Natl Lab Computat Engn & Energy Sci Grp Oak Ridge TN 37831 USA Sandia Natl Labs Dept Scalable Algorithms Albuquerque NM 87185 USA

We present Tpetra, a Trilinos package for parallel linear algebra primitives implementing the Petra object model. We describe Tpetra's design, based on generic programming via C++ templated types and template metaprogramming. We discuss some benefits of this approach in the context of scientific computing, with illustrations consisting of code and notable empirical results.

关键词： Generic programming scientific computing template metaprogramming shared-memory programming distributed-memory programming many-core computing

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Parallel compressive sampling matching pursuit algorithm for compressed sensing signal reconstruction with OpenCL

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JOURNAL OF SYSTEMS ARCHITECTURE 2017年 72卷 51-60页

作者： Huang, Fang Tao, Jian Xiang, Yang Liu, Peng Dong, Lei Wang, Lizhe Univ Elect Sci & Technol China Sch Resources & Environm Chengdu 611731 Peoples R China Univ Elect Sci & Technol China Inst Remote Sensing Big Data Big Data Res Ctr Chengdu 611731 Peoples R China Louisiana State Univ Ctr Computat & Technol Baton Rouge LA 70803 USA Deakin Univ Sch Informat Technol Geelong Vic 3216 Australia China Univ Geosci Sch Comp Sci Wuhan 430074 Peoples R China Chinese Acad Sci Inst Remote Sensing & Digital Earth Beijing 10094 Peoples R China

Compressive sensing (CS) is a new signal processing method, which was developed recent years. CS can sample signals with a frequency far below the Nyquist frequency. CS can also compress the signals while sampling, which can reduce the usage of resources for signal transmission and storage. However, the reconstruction algorithm used in the corresponding decoder is highly complex and computationally expensive. Thus, in some specific applications, e.g., remote sensing image processing for disaster monitoring, the CS algorithm usually cannot satisfy the time requirements on traditional computing platforms. Various studies have shown that many-core computing piatforms such as OpenCL are among the most promising platforms that are available for real-time processing because of their powerful floating-point computing capabilities. In this study, we present the design and implementation of parallel compressive sampling matching pursuit (CoSaMP), which is an OpenCL-based parallel CS reconstruction algorithm, as well as some optimization strategies, such as access efficiency, numerical merge, and instruction optimization. Based on experiments using remote sensing images with different sizes, we demonstrated that the proposed parallel algorithm can achieve speedups of about 41 times and 58 times on AMD HD7350 and NVIDIA K20Xm platforms, respectively, without modifying the application code. (C) 2016 Elsevier B.V. All rights reserved.

关键词： Compressive sensing CoSaMP Heterogeneous computing many-core computing OpenCL

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