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Applying Petri Nets to Modeling of many-core processor Self-Testing when Tests are Performed Randomly

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2013年第1期29卷 25-34页

作者： Mashkov, Viktor Barilla, Jiri Simr, Pavel Univ JE Purkine Fac Sci Dept Informat Usti Nad Labem Czech Republic

Today's many-core processors are manufactured in inherently unreliable technologies. Massively defective technologies used for production of many-core processors are the direct consequence of the feature size shrinkage in today's CMOS (complementary metal-oxide-semiconductor) technology. Due to these reliability problems, fault-tolerance of many-core processors becomes one of the major challenges. To reduce the probability of failures of many-core processors various fault tolerance techniques can be applied. The most preferable and promising techniques are the ones that can be easily implemented and have minimal cost while providing high level of processor fault tolerance. One of the promising techniques for detection of faulty cores, and consequently, for performing the first step in providing many-core processor fault tolerance is mutual testing among processor cores. Mutual testing can be performed either in a random manner or according to a deterministic scheduling policy. In the paper we deal with random execution of mutual tests. Effectiveness of such testing can be evaluated through its modeling. In the paper, we have shown how Stochastic Petri Nets can be used for this purpose and have obtained some results that can be useful for developing and implementation of testing procedure in many-core processors.

关键词： many-core processor Fault tolerance Mutual testing procedure Modeling tools

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Parallel deblocking filter for HEVC on many-core processor

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ELECTRONICS LETTERS 2014年第5期50卷 367-+页

作者： Yan, Chenggang Zhang, Yongdong Dai, Feng Wang, Xi Li, Liang Dai, Qionghai Chinese Acad Sci Inst Comp Technol Beijing Peoples R China Tsinghua Univ Beijing 100084 Peoples R China

High-efficiency video coding (HEVC) is the next generation standard of video coding. The deblocking filter (DF) constitutes a significant part of the HEVC decoder complexity. A three-step parallel framework (TPF) is proposed for the H. 264/AVC DF, which is also suitable for HEVC except the third step. The third step of the TPF is replaced with a directed acyclic graph-based order. Experiments show that the proposed method dramatically accelerates more than the state-of-the-art parallel method.

关键词： filtering theory video coding many-core processor DAG Video signal processing HEVC decoder Combinatorial mathematics parallel deblocking filter Microprocessor chips Image and video coding high-efficiency video coding H.264/AVC DF Microprocessors and microcomputers three-step parallel framework Filtering methods in signal processing directed graphs microprocessor chips directed acyclic graph TPF multiprocessing systems

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Nesting ring architecture of multichip optical network on chip for many-core processor systems

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OPTICAL ENGINEERING 2017年第3期56卷

作者： Li, Wenzhe Guo, Bingli Li, Xin Yin, Shan Zhou, Yu Huang, Shanguo Beijing Univ Posts & Telecommun State Key Lab Informat Photon & Opt Commun Beijing Peoples R China

Optical network on chip (ONoC) is an attractive solution for multicore/many-core processor systems due to its high power efficiency and enormous bandwidth. However, as increasing numbers of cores need to be interconnected, the scalability of a many-core processor on a single chip is limited by its process yield and power density. A multichip architecture is, therefore, proposed to improve the scalability of ONoC. In multichip architectures, the throughput and traffic delay rely on both the intrachip and interchip networks. To exploit the advantages of multichip systems, first we propose a multichip ONoC architecture for a many-core processor system that employs a nesting ring topology. The design principles of multichip systems of different sizes are then investigated to achieve higher throughput and lower delay. These principles include the number of chips and the number of cores per chip, which are considered jointly for the first time. Finally, we evaluate the performance of the proposed architecture, implemented in 240-core and 400-core systems, respectively, and compare it to two other traditional ONoC architectures with respect to throughput and end-to-end (ETE) delay. The results show that the proposed multichip system exhibits good scalability, achieves high throughput, and provides low ETE delay. (C) 2017 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： optical network on chip multichip system many-core processor

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Thermal-Aware On-Line Scheduler for 3-D many-core processor Throughput Optimization

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2014年第5期33卷 763-773页

作者： Yu, Cody Hao Lung, Chiao-Ling Ho, Yi-Lun Hsu, Ruei-Siang Kwai, Ding-Ming Chang, Shih-Chieh Natl Tsing Hua Univ Dept Comp Sci Hsinchu 300 Taiwan Ind Technol Res Inst Informat & Commun Res Labs Hsinchu 31040 Taiwan

3-D many-core processor (3-D MCP) has become an emerging technology to tackle the power wall problem due to rapidly increasing number of transistors. However, when maximizing the throughput of 3-D MCP, which is expressed as a weighted sum of the speeds, due to the inherent heat removal limitation, thermal issues must be taken into consideration. Since the temperature of a core strongly depends on its location in the 3-D IC, a proper task allocation can alleviate the thermal problem and improve the throughput. Nevertheless, conventional techniques require computationally intensive thermal simulation, which prohibits its usage from the online application. In this paper, we propose an efficient online task allocation and task migration algorithm attempting to maximize the throughput of 3-D MCP simultaneously, considering unfinished tasks left from the last scheduling interval and new incoming tasks of this scheduling interval. The results of our experiments show that our proposed method achieves a 20.82X runtime speedup. These results are comparable to the exhaustive solutions obtained from optimization-modeling software LINGO. In addition, on average, our throughput results, with and without consideration of unfinished tasks, are only 4.39% and 0.69% worse, respectively, than that of the exhaustive method. In 128 task-to-core allocations, our method takes only 0.951 ms, which is 59.39 times faster than that of the previous work.

关键词： 3-D integration many-core processor migration penalty task allocation task migration temperature uniformity thermal aware throughput optimization

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A Novel Macro-Block Group Based AVS Coding Scheme for many-core processor

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2011年第1期65卷 129-145页

作者： Wang, Zhenyu Liang, Luhong Yang, Guolei Zhang, Xianguo Sun, Jun Zhao, Debin Gao, Wen Peking Univ Beijing 100871 Peoples R China Chinese Acad Sci Inst Comp Technol Key Lab Intelligent Informat Proc Beijing 100190 Peoples R China Harbin Inst Technol Harbin 150001 Peoples R China

Implementation of video coding systems such as H.264/AVC and AVS on multi-core and many-core platforms is attracting much attention. The slice-level parallelism is popular in parallel video coding for its simplicity and flexibility, however, the video quality loses greatly since the partitioning of slices breaks the dependency between macro-blocks, especially on multi-core or many-core platforms. To address this problem, we propose a Macro-Block Group (MBG) parallel scheme for parallel AVS coding. In the proposed scheme, video frames are equally divided into rectangular MBG regions;each MBG consists of more rows and less columns of macro-blocks than the slice-level scheme. Given that MBG is not syntactically supported by AVS, a vertical partitioning scheme is introduced. Additionally, we use mode confining and motion vector difference adjusting techniques to keep consistent with the standard. Two MBG parallel schemes (5 x 9 MBG partition and 8 x 7 MBG partition) are developed on a TILE64 many-core platform, where P/B frames use the MBG parallel scheme and I frames use the macro-block-level parallelism. Experimental results show that the proposed scheme of 5 x 9 MBG partition can achieve a reduction of 52% (IPPP) and 41% (IBBP) quality loss while keeping the same speed-up compared with the slice-level parallelism. With more cores employed, the scheme of 8 x 7 MBG partition gains 23.9 times of speed-up compared with the single-core implementation and achieves similar coding performance as the 5 x 9 scheme.

关键词： Parallel video encoding Macro-block group many-core processor

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AMT: asynchronous in-place matrix transpose mechanism for sunway many-core processor

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JOURNAL OF SUPERCOMPUTING 2022年第7期78卷 9456-9474页

作者： Chen, Zhengbo Wang, Di Yu, Qi Zheng, Fang Guo, Feng Chen, Zuoning Informat Engn Univ Zhengzhou Peoples R China State Key Lab Math Engn & Adv Comp Wuxi Jiangsu Peoples R China Chinese Acad Engn Beijing Peoples R China

Matrix multiplication is widely used in a variety of application domains. When the input matrices and the product differ in the memory format, matrix transpose is required. The efficiency of matrix transpose has a non-negligible impact on performance. However, the state-of-the-art software solution and its optimizations suffer from low efficiency due to frequent interference to main pipeline and their inability to achieve parallel matrix transpose and multiplication. To address this issue, we propose AMT, an asynchronous and in-place matrix transpose mechanism based on C2R algorithm, to efficiently perform matrix transpose. AMT performs matrix transpose in an asynchronous processing module and uses two customized asynchronous matrix transpose instructions to facilitate processing. We implement the logic design of AMT using RTL and verify its correctness. Simulation results show that AMT achieves an average of 1.27x (up to 1.48x) speedup over a state-of-the-art software baseline, and is within 95.4% of an ideal method. Overhead analysis shows that AMT only incurs small area overhead and power consumption.

关键词： Matrix transpose Matrix Multiplication C2R algorithm many-core processor

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Exploration of Efficient many-core processor for Dual-Polarization and Sympathetic Plucked String Model

Exploration of Efficient Many-Core Processor for Dual-Polari...

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5th International Conference on Information Science and Applications (ICISA)

作者： Kang, Myeongsu Kim, Jong-Myon Univ Ulsan Dept Elect Engn Ulsan 680749 South Korea

ISBN: (纸本)9781479944415

Despite the fact that physics-based sound synthesis is becoming more and more efficient in rich and natural high-quality sound synthesis, its high computational complexity limits its use in portable devices. This constraint motivated research on parallel processing architectures that support the physics-based sound synthesis of musical instruments. Since no general consensus has been reached which grain sizes of many-core processors and memories provide the most efficient operation for sound synthesis, this paper explores a many-core processor for varying its PE configurations. To find the optimal PE configuration, each PE configuration is evaluated in terms of execution time, system power, and area. Experimental results indicate that the most efficient operation in order to synthesize 44,100 six-note polyphonic acoustic guitar sound sampled at 44.1 kHz is achieved as the number of PEs equals to 192. Likewise, all PE configurations used in this study are satisfied with the system requirements to implement sound synthesis on a portable device.

关键词： Design space exploration many-core processor Parallel processing architecture Physics-based sound synthesis

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swGBDT: Efficient Gradient Boosted Decision Tree on Sunway many-core processor 6th

swGBDT: Efficient Gradient Boosted Decision Tree on Sunway M...

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6th Asian Supercomputing Frontiers Conference (SCFA)

作者： Yin, Bohong Li, Yunchun Dun, Ming You, Xin Yang, Hailong Luan, Zhongzhi Qian, Depei Beihang Univ Sch Comp Sci & Engn Beijing Peoples R China Beihang Univ Sch Cyber Sci & Techonol Beijing Peoples R China

ISBN: (纸本)9783030488420;9783030488413

Gradient Boosted Decision Trees (GBDT) is a practical machine learning method, which has been widely used in various application fields such as recommendation system. Optimizing the performance of GBDT on heterogeneous many-core processors exposes several challenges such as designing efficient parallelization scheme and mitigating the latency of irregular memory access. In this paper, we propose swGBDT, an efficient GBDT implementation on Sunway processor. In swGBDT, we divide the 64 CPEs in a core group into multiple roles such as loader, saver and worker in order to hide the latency of irregular global memory access. In addition, we partition the data into two granularities such as block and tile to better utilize the LDM on each CPE for data caching. Moreover, we utilize register communication for collaboration among CPEs. Our evaluation with representative datasets shows that swGBDT achieves 4.6x and 2x performance speedup on average compared to the serial implementation on MPE and parallel XGBoost on CPEs respectively.

关键词： Gradient Boosted Decision Tree many-core processor Performance optimization

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On-Chip Scan-Based Test Strategy for a Dependable many-core processor Using a NoC as a Test Access Mechanism

On-Chip Scan-Based Test Strategy for a Dependable Many-Core ...

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13th Euromicro Conference on Digital System Design on Architectures, Methods and Tools

作者： Zhang, Xiao Kerkhoff, Hans G. Vermeulen, Bart Univ Twente CTIT Testable Design & Test Integrated Syst Grp Enschede Netherlands NXP Semicond Distributed Syst Architectures Grp Res Adv Applicat Eindhoven Netherlands

ISBN: (纸本)9780769541716

Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated into the SoC to function as an ATE. This paper introduces the reuse of a Network-on-Chip as a test access mechanism. Since the scan-based test is performed on-chip via the NoC at application run-time, it needs to share the NoC bandwidth with other applications. Instead of reserving sufficient NoC bandwidth for the test, the authors propose a novel way to carry out scan-based tests by dynamically pausing and resuming the test data flow to accommodate the fluctuating communication bandwidth available on the NoC. The test stimuli application and test response collection processes are decoupled to meet the global timing constraint. The many-core processor, HP and the NoC have been implemented in synthesizable VHDL. Simulation results show the correct application of standard structural test patterns to the processing tiles and the test response collection at run-time using the proposed approach.

关键词： Scan-based test dependability many-core processor reconfiguration test wrapper network-on-chip (NoC) test access mechanism (TAM)

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Federated Learning Platform on Embedded many-core processor with Flower 3

Federated Learning Platform on Embedded Many-core Processor ...

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IEEE 3rd Real-Time and Intelligent Edge Computing Workshop (RAGE)

作者： Hasumi, Masahiro Azumi, Takuya Saitama Univ Grad Sch Sci & Engn Saitama Japan

ISBN: (纸本)9798350363357;9798350363340

In the emerging field of autonomous vehicle development, the role of artificial intelligence, particularly deep learning (DL), has garnered significant interest. This growing interest has led to extensive studies in using cameras and other onboard sensors for the critical task of object detection and recognition in these vehicles. A major concern, however, is the sensitive nature of the training data, which poses privacy risks when centralized on a server. Furthermore, as the demand for privacy protection increases, power consumption may increase rapidly. To address these issues, this paper proposes Federated Learning (FL) for DL on an embedded many-core processor. This study provides an implementation of FL, aiming to enhance privacy protection and energy efficiency in autonomous vehicle development. The experimental results of the proposed FL platform demonstrate that it offers significant improvements in processing speed and power consumption, suggesting an enhanced performance compared to existing edge devices.

关键词： Federated learning many-core processor deep neural network embedded systems

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