In this paper, an energy- and traffic-balance-aware mapping algorithm from IP cores to nodes in a network is proposed for application-specific Network-on-Chip(NoC). The multi-objective optimization model is set up by ...
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In this paper, an energy- and traffic-balance-aware mapping algorithm from IP cores to nodes in a network is proposed for application-specific Network-on-Chip(NoC). The multi-objective optimization model is set up by considering the NoC architecture, and addressed by the proposed mapping algorithm that decomposes mapping optimization into a number of scalar subproblems simultaneously. In order to show performance of the proposed algorithm, the application specific benchmark is applied in the simulation. The experimental results demonstrate that the algorithm has advantages in energy consumption and traffic balance over other algorithms.
Three-dimensional network on chip (3D NoC) is developed based on three-dimensional integrated circuit, system on chip and two-dimensional network on chip. The 3D NoC is mainly used to solve the problems such as commun...
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Three-dimensional network on chip (3D NoC) is developed based on three-dimensional integrated circuit, system on chip and two-dimensional network on chip. The 3D NoC is mainly used to solve the problems such as communication bottleneck of highly integrated chips. mapping of 3D NoC is a key problem in the research area of 3D NoC. The authors proposed a low-power mapping algorithm based on quantum-behaved particle swarm optimization. Simulation results show that the proposed algorithm can significantly reduce power consumption, but with large-scale application characteristic graph, the efficiency of power optimization cannot be improved very much. To solve this problem, a low-power mapping algorithm for 3D NoC based on diversity-controlled quantum-behaved particle swarm optimization is proposed in this paper. Simulation results show that for large-scale application characteristic graph, this algorithm is able to maintain a stable power optimization efficiency (4.08-8.04%) and converges much faster.
This paper presents the ABeeMap, a new approach to FPGA technology mapping. The mapper is based on a hybrid approach that uses pareto-dominance based asynchronous multi-objective Artificial Bee Colony associated with ...
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ISBN:
(纸本)9781467394192
This paper presents the ABeeMap, a new approach to FPGA technology mapping. The mapper is based on a hybrid approach that uses pareto-dominance based asynchronous multi-objective Artificial Bee Colony associated with specific heuristics of the problem in order to find better trade-off results among area, performance and power consumption. In a set of 20 designs, we find that in comparison to state-of-the-art technology mapping, our approach is able to reduce the LUT counts and the edge counts. Placing and routing the resulting netlist leads to reduction in the configurable logic blocks count, increasing in estimated operation frequency and reduction in energy consumption.
In Distributed Virtual Environment (DVE) systems, a distributed server infrastructure is often used to reduce the latency between servers and clients. Under this infrastructure, mapping clients to proper servers is on...
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ISBN:
(纸本)9780769538594
In Distributed Virtual Environment (DVE) systems, a distributed server infrastructure is often used to reduce the latency between servers and clients. Under this infrastructure, mapping clients to proper servers is one of the key issues for improving the interactivity and overall performance. Most traditional methods of mapping the clients to servers only consider the load balancing problem. However, there are two other important aspects that should be involved: the physical world integrity and the virtual world integrity. In this work, we propose a novel mapping algorithm which takes care of all three aspects at the same time. The algorithm converts the mapping problem into cutting stage and matching stage to get optimal result with polynomial complexity. The experimental results show that our algorithm improves the overall performance of DVE systems significantly.
Network-on-chip(NoC) mapping algorithms significantly affect NoC system performance in terms of communication cost and energy consumption. For a specific application represented by a task graph, this paper proposes ...
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ISBN:
(纸本)9781538619797;9781538619780
Network-on-chip(NoC) mapping algorithms significantly affect NoC system performance in terms of communication cost and energy consumption. For a specific application represented by a task graph, this paper proposes an energyaware mapping algorithm that searches for the mapping solution with best communication locality and therefore lowest energy consumption. During the search procedure, we employ a simulation-free, communication locality-based energy model to evaluate the quality of each candidate mapping. By iteratively updating the best candidate mapping using a greedy search heuristic, the search procedure converges to an mapping decision with optimal energy efficiency in the search space. Compared with the round-robin mapping strategy, the proposed method is capable of exploring energy-efficient mapping decision for various applications as well as network sizes.
Fast aging of components has become one of the major concerns in Systems-on-Chip with further scaling of the submicron technology. This problem accelerates when combined with improper working conditions such as unbala...
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ISBN:
(纸本)9781509006021
Fast aging of components has become one of the major concerns in Systems-on-Chip with further scaling of the submicron technology. This problem accelerates when combined with improper working conditions such as unbalanced components' utilization. Considering the mapping algorithms in the Networks-on-Chip domain, some routers/links might be frequently selected for mapping while others are underutilized. Consequently, the highly utilized components may age faster than others which results in disconnecting the related cores from the network. To address this issue, we propose a mapping algorithm, called lifetime-aware neighborhood allocation (LaNA), that takes the aging of components into account when mapping applications. The proposed method is able to balance the wear-out of NoC components, and thus extending the service time of NoC. We model the lifetime as a resource consumed over time and accordingly define the lifetime budget metric. LaNA selects a suitable node for mapping which has the maximum lifetime budget. Experimental results show that the lifetime-aware mapping algorithm could improve the minimal MTTF of NoC around 72.2%, 58.3%, 46.6% and 48.2% as compared to NN, CoNA, WeNA and CASqA, respectively.
Network-on-chip(No C) emerged as a promising alternative to the bus and point-to-point communication architectures. Recently 3D No C become a hot *** complex 3D No Cs will generate a large amount of data to deal with,...
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ISBN:
(纸本)9781467397209
Network-on-chip(No C) emerged as a promising alternative to the bus and point-to-point communication architectures. Recently 3D No C become a hot *** complex 3D No Cs will generate a large amount of data to deal with, No Cs suffer from intermittent congestions and link overflows, especially when the network bandwidth is limited by the area and energy budget. In this paper, we explore a technique for balance link bandwidth based mapping algorithm dedicated to No C. After mapping we double the link bandwidth according to the high-bandwidth allocation through the network busy nodes, while the remaining links bandwidth assignment unchanged. Experiments results show that the network average delay is reduced by 25%through doubling the central loop bandwidth.
This paper develops an fuzzy mapping methodology for brightness improvement of color display systems using white sub-pixels. Based on human vision discrimination, three novel white sub-pixel filter structures without ...
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ISBN:
(纸本)9781424400997
This paper develops an fuzzy mapping methodology for brightness improvement of color display systems using white sub-pixels. Based on human vision discrimination, three novel white sub-pixel filter structures without loss of original resolution are presented to enhance brightness of conventional stripe, Delta and PenTile color filter architectures. A new mapping fuzzy algorithm using RGB sub-pixel data around a white subpixel is proposed to improve overall image quality. Numerous simulation results are provided to show the efficacy of the proposed method for improving conventional stripe, delta and PenTile display systems. Experimental results are described which has been conducted to show that the proposed color display system performs well for electronic consumer products, such as notebooks, personal digital assistants, and mobile phone, etc.
This paper develops methodology and technique for brightness improvement of color display systems using white sub-pixels. Based on human vision discrimination, three novel white sub-pixel filter structures without los...
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ISBN:
(纸本)9780780387300
This paper develops methodology and technique for brightness improvement of color display systems using white sub-pixels. Based on human vision discrimination, three novel white sub-pixel filter structures without loss of original resolution are presented to enhance brightness of conventional stripe, Delta and PenTile color filter architectures, A new mapping algorithm fusing RGB sub-pixel data around a white sub-pixel is proposed to improve overall image quality. Numerous simulation results are provided to show the feasibility and efficacy of the proposed method for improving conventional stripe, delta and PenTile display systems. Experimental result is described which has been conducted to show that the proposed color display system performs well for electronic consumer products, such as notebooks, personal digital assistants, and mobile phone, etc.
Network-on-chip (NoC) mapping algorithms significantly affect NoC system performance in terms of communication cost and energy consumption. For a specific application represented by a task graph, this paper proposes a...
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Network-on-chip (NoC) mapping algorithms significantly affect NoC system performance in terms of communication cost and energy consumption. For a specific application represented by a task graph, this paper proposes an energy-efficient mapping algorithm that searches for the mapping decision with best communication locality and therefore lowest energy consumption. To this end, we formulate the concerned mapping problem as an optimization model, and propose an effective meta-heuristic algorithm to solve the formulated optimization model. During the mapping procedure, we employ a simulation-free, communication probability-based energy model to evaluate the quality of each candidate mapping. By iteratively updating the best explored mapping decision using a meta-heuristic search strategy, the mapping procedure can eventually identify an mapping decision with optimal energy efficiency in the search space. The proposed mapping algorithm has been verified on NoC systems of different sizes using a variety of benchmark applications. Simulation results demonstrate that the mapping decision produced by this algorithm achieves an up to 23% energy reduction compared with the traditional round-robin strategy.
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