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Medical Data Large-scale Processing Technology Based on march algorithm

Procedia Computer Science 2025年 259卷 572-580页

作者： Weisong He Pingdu Municipal Health Bureau Pingdu 266700 Qingdao Shandong China

With the rapid development of medical informatization, the existing hospital information system and electronic health record system can no longer meet the demand for storing and processing massive medical data, analyzing and mining, and diversified medical data services. After the generation and collection of massive medical data, how to effectively store heterogeneous, massive, real-time, and diverse data to meet the rapid and precise response to complex medical data is an urgent problem to be solved. How to utilize data mining technology to deeply analyze the massive medical big data and provide valuable medical big data services for patients, so as to realize "preventing diseases before they occur", is an important problem in the current medical research. This article analyzed the medical data large-scale processing technology based on the march algorithm and explored its application and advantages in the medical field. The march algorithm is an efficient algorithm for processing large-scale data, which can effectively improve data processing speed and efficiency by dividing the data into small blocks for parallel processing. The experimental results indicated that as the number of files increased from 10000 to 50000, the memory usage of the march algorithm was relatively low within the same range, increasing from 0.68 to 13.26.

关键词： Medical Data march algorithm Data Silos Electronic Medical Records

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An Automation Program for march algorithm Fault Detection Analysis

An Automation Program for March Algorithm Fault Detection An...

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IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) / IEEE Conference on Postgraduate Research in Microelectronics and Electronics (PRIMEASIA)

作者： Jidin, Aiman Zakwan Hussin, Razaidi Fook, Lee Weng Mispan, Mohd Syafiq Univ Malaysia Perlis Fac Elect Engn Technol Arau Malaysia Emerald Syst Design Ctr George Town Malaysia Univ Tekn Malaysia Melaka Fac Elect & Elect Engn Technol Melaka Malaysia

ISBN: (纸本)9781665439169

The efficiency of a Memory BIST for embedded memory testing depends on the fault coverage of the implemented test algorithm. A fault simulator is necessary to analyze. The fault detection performance analysis on a march algorithm is indispensable to determine its fault coverage. This manual analysis process is very tedious and time-consuming, and thus, a fault simulator is necessary to perform fault simulation on a memory model. This paper presents the development of an automation program to analyze a march algorithm fault detection performance autonomously, without performing fault simulation. It works by identifying the pair of sensitizer and detector of each fault model, the memory cells values trend, and finally producing a detailed fault detection analysis result and the fault coverage. The program test on march SR and march CL algorithms produced accurate fault detection analysis and the expected fault coverages, which were completed in less than 3 ms.

关键词： Memory BIST Memory Fault Models march algorithm Memory Fault Detection Analysis Automation

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Reduced march SR algorithm for Deep-Submicron SRAM Testing

Reduced March SR Algorithm for Deep-Submicron SRAM Testing

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15th IEEE International Conference on Semiconductor Electronics (ICSE)

作者： Jidin, Aiman Zakwan Hussin, Razaidi Mispan, Mohd Syafiq Fook, Lee Weng Ying, Loh Wan Univ Malaysia Perlis Fac Elect Engn Technol Arau Malaysia Univ Tekn Malaysia Melaka Fak Teknol Kejuruteraan Elekt & Elekt Melaka Malaysia Emerald Syst Design Ctr George Town Malaysia

ISBN: (数字)9781665482462

ISBN: (纸本)9781665482462

Memory Built-In Self-Test (BIST) is a common method to test embedded memories on a chip owing to its fast and low-cost testing. Its efficiency depends on the complexity and the fault coverage offered by its implemented test algorithm. Test algorithms with higher complexities result in longer test times and higher costs. Hence, many research works were proposed to reduce the complexity of the existing algorithm while preserving its fault coverage. This paper presents a method to reduce the march SR algorithm complexity (14N) by analyzing and removing redundant test operations from its test sequence. It was targeted for fault detection in deep-submicron SRAM. The newly produced march mSR algorithm, with IN complexity lesser than the march SR algorithm but offers the same coverage of the intended faults, was implemented in a Memory BIST controller. The simulations successfully validated its test time reduction, functionality, and fault coverage.

关键词： Design for Testability SRAM Memory BIST march algorithm Fault Detection

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A New Test algorithm and Fault Simulator of Simplified Three-Cell Coupling Faults for Random Access Memories

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IEEE ACCESS 2024年 12卷 109218-109229页

作者： Wu, Tiancheng Fan, Weikang Gu, Yuefeng Fan, Feifan Li, Qiuhong Xiamen Univ Sch Elect Sci & Engn Xiamen 361005 Peoples R China Xiamen Univ Pen Tung Sah Inst Micronano Sci & Technol Xiamen 361005 Peoples R China

This study introduces a novel algorithm for the detection of three-cell coupling faults, march ML3C, along with a simulator, TCFS. The march ML3C algorithm targets the detection of single-port, static, and unlinked three-cell coupling faults within bit-oriented random access memory (RAM). march ML3C improves the coverage of three-cell coupling faults to 100%, with a complexity of only 58n (n is the number of memory cells), which is lower than that of most similar algorithms. Furthermore, to solve the problem of none of the existing tools supporting the simulation of three-cell coupling faults, this study designs and implements TCFS, which can quickly simulate all march-type algorithms and calculate the coverages for three-cell coupling faults, thus achieving the purpose of software simulation of the algorithms. The simulation results of march ML3C and other similar algorithms using TCFS are also presented in this paper.

关键词： Couplings Random access memory Complexity theory Memory management Software algorithms Testing Task analysis Design for testability fault simulator march algorithm memory testing three-cell coupling fault

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Structured DFT Development Approach for Chisel-Based High Performance RISC-V Processors 7

Structured DFT Development Approach for Chisel-Based High Pe...

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7th IEEE International Test Conference in Asia (ITC-Asia)

作者： Zhang, Bin Cai, Ye He, Zhiheng Liang, Sen He, Wei Shenzhen Univ Shenzhen Peoples R China Beijing Inst Open Source Chip Beijing Peoples R China Chinese Acad Sci Inst Comp Beijing Peoples R China Pengcheng Lab Shenzhen Peoples R China

ISBN: (纸本)9798350312812

Research has shown that agile language Chisel and related agile design methodology is promising to sustain the scaling computing performance in a more efficient way. Design For Test, as an economical and effective method for chip production testing, must be integrated into the agile development system to meet the requirements of mass production. Due to the lack of support for the traditional EDA toolchain, chip development through Chisel has not been widely accepted in the industry. This paper is based on the research of XiangShan, an open-source project for RISC-V high-performance processor. XiangShan establishes a structured DFT(degisn for test) development approach and Chisel-based DFT agile design flow. XiangShan develops a flexible chisel-based XS-shared bus mbist interface to improve design PPA and proposes the marchSLD algorithm to enhance defect detection in the FinFet process node. XiangShan's DFT development Approach is moving towards hierarchical, flexible, and reliable in two generations of processors. Experimental results show that the optimized Chisel-based DFT design flow can support agile development requirements and achieve industry-competitive performance.

关键词： Chisel Design For Test Shared bus MBIST march algorithm

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Fault Modeling and Efficient Testing of Memristor-Based Memory

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2021年第11期68卷 4444-4455页

作者： Liu, Peng You, Zhiqiang Wu, Jigang Liu, Bosheng Han, Yinhe Chakrabarty, Krishnendu Guangdong Univ Technol Sch Comp Guangzhou 510006 Peoples R China Hunan Univ Coll Comp Sci & Elect Engn Key Lab Embedded & Network Comp Hunan Prov Changsha 410082 Hunan Peoples R China Chinese Acad Sci Inst Comp Technol Key Lab Comp Syst & Architecture Beijing 100190 Peoples R China Duke Univ Dept Elect & Comp Engn Durham NC 27708 USA

Memristor-based memory technology is one of the emerging memory technologies, which is a potential candidate to replace traditional memories. Efficient test solutions are required to enable the quality and reliability of such products. In previous works, fault models are caused by open, short and bridge defects and parametric variations during the fabrication. However, these fault models cannot describe the bridge defects that cause the state of the faulty cell to an undefined state. In this paper, we analyze the different effects of bridge defects and aggregate their faulty behavior into new fault models, undefined coupling fault and dynamic undefined coupling fault. In addition, an enhanced march algorithm is designed to detect all the modeled faults. In one resistor crossbar with N memristors, the enhanced march algorithm requires 8N write and 7N read operations with negligible hardware overhead. To reduce the test time, a march RC algorithm is proposed based on read operations with new reference currents, which requires 4N + 2 write and 6N read operations. Analytical results show that the proposed test algorithms can detect all the modeled faults outperforming all the previous methods. Subsequently, a Design-for-Testability scheme is proposed to implement march RC algorithm with a little area overhead.

关键词： Electrical defects fault model defect-oriented testing march algorithm non-volatile memory

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Architecture for an efficient MBIST using modified march-y algorithms to achieve optimized communication delay and computational speed

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INTERNATIONAL JOURNAL OF PERVASIVE COMPUTING AND COMMUNICATIONS 2021年第1期17卷 135-147页

作者： Nisha, O. S. Sivasankar, K. Lourdes Matha Coll Sci & Technol Dept CSE Thiruvananthapuram Kerala India Noorul Islam Coll Engn Dept IT Kanyakuinari India

Purpose In this work, an efficient architecture for memory built in self-test (MBIST) that incorporates a modified march Y algorithm using concurrent technique and a modified linear feedback shift register (LFSR)-based address generator is proposed. Design/methodology/approach Built in self-test (BIST) is emerging as the essential ingredient of the system on chip. In the ongoing high speed, high tech sophistication technology of the very large-scale integrated circuits, testing of these memories is a very tedious and challenging job, since the area overhead, the testing time and the cost of the test play an important role. Findings With the efficient service of the adapted architecture, switching activity is considerably cut down. As the switching activity is in direct proportion to the power consumed scaling down, the switching process of the address generator inevitably leads to the reduction in power consumption of the MBIST. Originality/value To improve the yield and fault tolerance of on-chip memories without degradation on its performance self-repair mechanisms can be implemented on chip.

关键词： Computational speed march algorithm MBIST Optimized communication delay

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A Novel BIST algorithm for Low-voltage SRAM 3

A Novel BIST Algorithm for Low-voltage SRAM

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IEEE International Test Conference in Asia (ITC-Asia)

作者： Cai, Zhikuang Wang, Ying Liu, Shihuan Lv, Kai Wang, Zixuan Nanjing Univ Posts & Telecommun Coll Elect & Opt Engn 9 Wenyuan Rd Nanjing 210003 Peoples R China

ISBN: (纸本)9781728147185

A novel Built-In Self-Test (BIST) algorithm is proposed in this paper, which is used for testing low-voltage SRAM. The algorithm is the improvement of march C+ algorithm, which integrates the continuous write 0 and write 1 operations to cover more fault models like Read Destructive Coupling Fault (CFrd), Write Destructive Coupling Fault (CFwd) and Write Disturb Fault. Consequently, higher fault coverage is achieved than traditional march algorithm. The proposed algorithm is implemented by user defined algorithm (UDA) of Mentor tools. In order to verify the effectiveness of the algorithm, a low-voltage 8T SRAM chip is designed and tested based on SMIC 40nm LL CMOS process. Simulation results show that the proposed BIST algorithm named march-LV for low-voltage SRAM arrays covers 100% target faults. The test results further verify the feasibility of the algorithm.

关键词： Low-voltage SRAM Fault Model march algorithm BIST

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Logic operation-based DFT method and 1R memristive crossbar march-like test algorithm

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IEICE ELECTRONICS EXPRESS 2015年第23期12卷

作者： Liu, Peng You, Zhiqiang Kuang, Jishun Hu, Zhipeng Wang, Weizheng Hunan Univ Coll Comp Sci & Elect Engn Changsha 410082 Hunan Peoples R China Changsha Univ Sci & Technol Coll Comp & Commun Engn Changsha Peoples R China

As an attractive option of future non-volatile memories (NVM), resistive random access memory (RRAM) has attracted more attentions. Due to its high density and low power, one memristor (1R) crossbar is a dominant RRAM structure. In this paper, we propose a logic operation-based design for testability (DFT) architecture for 1R crossbar testing. In this architecture, memristor-aided logic (MAGIC) NOR gates are embedded to check whether all the cells in the crossbar are 0 s or not at a time. A march-like test algorithm is also presented for the proposed architecture, which covers all modeled faults. The test time is reduced drastically with a little area overhead.

关键词： memristive crossbar RRAM DFT march algorithm logic operation

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A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory

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ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS 2015年第1期12卷 1–18页

作者： Ghofrani, Amirali Lastras-Montano, Miguel-Angel Gaba, Siddharth Payvand, Melika Lu, Wei Theogarajan, Luke Cheng, Kwang-Ting Univ Calif Santa Barbara Dept Elect & Comp Engn Santa Barbara CA 93106 USA Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

Recent advances in access-transistor-free memristive crossbars have demonstrated the potential of memristor arrays as high-density and ultra-low-power memory. However, with considerable variations in the write-time characteristics of individual memristors, conventional fixed-pulse write schemes cannot guarantee reliable completion of the write operations and waste significant amount of energy. We propose an adaptive write scheme that adaptively adjusts the write pulses to address such variations in memristive arrays, resulting in 7x-11x average energy saving in our case studies. Our scheme embeds an online monitor to detect the completion of a write operation and takes into account the parasitic effect of line-shared devices in access-transistor-free crossbars. This feature also helps shorten the test time of memory march algorithms by eliminating the need of a verifying read right after a write, which is commonly employed in the test sequences of march algorithms.

关键词： Adaptive Write Scheme Access-Transistor-Free Leakage-Current Filtering Low-Power march algorithm Memory Testing Memristive Crossbar Memristor Online Resistance Monitoring ReRAM Variation-Aware Design

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