With recent advances in semiconductor technologies, the design and use of memories for realizing complex system-on-a-chip (SoC) is very widespread. The growing need for storage in computer, communication, and network ...
详细信息
With recent advances in semiconductor technologies, the design and use of memories for realizing complex system-on-a-chip (SoC) is very widespread. The growing need for storage in computer, communication, and network appliances has motivated new advancements in faster and more efficient ways to test memories. Efficient testing schemes for single-port memories have been readily available. Multiport memories are widely used in multiprocessor systems, telecommunication application-specific integrated circuits (ASICs), etc. Research papers which define multiport memory fault models and give march tests for the same are currently available. However, little work has been done to use the power of serial interfacing for testing multiport memories. In this paper, we develop a powerful test architecture for two-port memories using the serial interfacing technique. Based on the serial testing mechanism, we propose new march algorithms which can prove effective to reduce hardware cost considerably for a chip with many two-port memories. Once we understand how serial interfacing helps test two-port memories, one possible extension is to use serial interfacing for p-port memories (p > 2). The proposed method based on the serial interfacing technique has the advantages of high fault coverage, low hardware overhead, and tolerable test application time.
The authors present test algorithms for go/no-go and diagnostic test of memories, covering neighborhood pattern-sensitive faults (NPSFs). The proposed test algorithms are march based, which have linear time complexity...
详细信息
The authors present test algorithms for go/no-go and diagnostic test of memories, covering neighborhood pattern-sensitive faults (NPSFs). The proposed test algorithms are march based, which have linear time complexity and result in a simple built-in self-test (BIST) implementation. Although conventional march algorithms do not generate all neighborhood patterns to test the NPSFs, they can be modified by using multiple data backgrounds such that all neighborhood patterns can be generated. The proposed multibackground march algorithms have shorter test lengths than previously reported ones, and the diagnostic test algorithm guarantees 100% diagnostic resolution for NPSFs and conventional RAM faults. Based on the proposed algorithms, the authors also present a cost-effective BIST design. The BIST circuit is programmable, and it supports march algorithms, including the proposed multibackground one.
We present a new transparent SRAM test algorithm, which uses dynamic power supply current. The proposed test scheme employs the dynamic power supply current instead of making signatures, so that it does not need the a...
详细信息
ISBN:
(纸本)0769518257
We present a new transparent SRAM test algorithm, which uses dynamic power supply current. The proposed test scheme employs the dynamic power supply current instead of making signatures, so that it does not need the additional steps and additional hardware to generate signature. This paper describes how to convert a traditional march algorithm to a transparent one. The transformed algorithm is much simpler and the test time can be reduced very much. In addition, it can detect some additional faults that the original algorithm cannot detect.
A new efficient test approach of functional faults in word-oriented content addressable memories (CAM) is presented. New functional fault models of CAM based on physical defects are given, expect for traditional funct...
详细信息
ISBN:
(纸本)0769518257
A new efficient test approach of functional faults in word-oriented content addressable memories (CAM) is presented. New functional fault models of CAM based on physical defects are given, expect for traditional functional fault models for SRAM. All functional fault of CAM are classified into Or Faults (ORFs) and And Faults (ANDFs). To test intra-word and inter-word faults, different data background sequences for word-oriented CAM are proposed. A whole test strategy include three steps is presented to test, word-oriented dual-port CAMs thoroughly.
In this correspondence, we propose an effective approach to integrate 40 existing march algorithms into an embedded low hardware overhead test pattern generator to test the various kinds of word-oriented memory cores....
详细信息
In this correspondence, we propose an effective approach to integrate 40 existing march algorithms into an embedded low hardware overhead test pattern generator to test the various kinds of word-oriented memory cores. Each march algorithm is characterized by several sets of up/down address orders, read/write signals, read/write data, and lengths of read/write operations. These characteristics are stored on chip so that any desired march algorithm can be generated with very little external control. An efficient procedure to reduce the memory storage for these characteristics is presented. We use only two programmable cyclic shift registers to generate the various read/write signals and data within the steps of the algorithms. Therefore, the proposed pattern generator is capable of generating any march algorithm, vith small area overhead.
Functional tests for content-addressable memories (CAM's) are presented in this paper. In addition to several traditional functional fault models for RAM's, we also consider the fault models based on physical ...
详细信息
Functional tests for content-addressable memories (CAM's) are presented in this paper. In addition to several traditional functional fault models for RAM's, we also consider the fault models based on physical defects, such as shorts between two circuit nodes and transistor stuck-on and stuck-open faults. Accordingly, several functional fault models are proposed. In order to make our approach suited to various application-specific CAM's, we propose tests which require only three fundamental types of operation (i.e., write, erase, and compare), and the test results can be observed entirely from the single-bit Hit output. A complete, compact test is also proposed, which has low complexity and is suitable for modern high-density and large-capacity CAMs-it requires only 2N + 3w + 2 compare operations and 8N write operations to cover the functional fault models discussed, where N is the number of words and w is the word length.
暂无评论