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27th Design, Automation and test in Europe Conference and Exhibition (DATE)

作者： Ammoura, Lila Flottes, Marie-Lise Girard, Patrick Noel, Jean-Philippe Virazel, Arnaud LIRMM Univ Montpellier CNRS F-34392 Montpellier France Univ Grenoble Alpes CEA LIST F-38000 Grenoble France

ISBN: (纸本)9798350348606;9783981926385

The shift towards data-centric computing paradigms has given rise to new architectural approaches aimed at minimizing data movement and enhancing computational efficiency. In this context, In-Memory Computing (IMC) architectures have gained prominence for their ability to perform processing tasks within the memory array, reducing the recourse to data transfers. However, the susceptibility of these new paradigms to manufacturing defects poses a critical test challenge. This paper presents a novel march-like test algorithm for 8T SRAM-based IMC architectures, addressing the imperative need for comprehensive read port related defect coverage. The proposed algorithm achieves complete coverage of potential read port defects while maintaining the level of complexity equivalent to existing state-of-the-art test solutions.

关键词： In-Memory Computing 8T SRAM bitcell testing march test algorithm DfT

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Novel march test algorithm Optimization Strategy for Improving Unlinked Faults Detection

Novel March Test Algorithm Optimization Strategy for Improvi...

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IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) / IEEE Conference on Postgraduate Research in Microelectronics and Electronics (PRIMEASIA)

作者： Jidin, Aiman Zakwan Hussin, Razaidi Mispan, Mohd Syafiq Fook, Lee Weng Univ Malaysia Perlis Fac Elect Engn Technol Arau Malaysia Univ Tekn Malaysia Melaka Fac Elect & Elect Engn Technol Melaka Malaysia Emerald Syst Design Ctr George Town Malaysia

ISBN: (纸本)9781665439169

march-series test algorithms have proven to be popular choices for Memory BIST implementation, owing to their simplicity yet having a good fault coverage. However, march test algorithms with low test complexities are incapable to detect some unlinked static Single-Cell faults and many Double-Cell faults. This paper presents a new optimization strategy to improve the fault coverage of the existing march algorithms by detecting the previously undetectable Single-Cell faults and Double-Cell faults. It is achieved by optimizing the test operation sequences of the existing march test algorithms through an automation program, to achieve higher fault coverage while maintaining the same test complexity as the original march algorithm. Performance analysis shows that the fault coverage of march LR and march SR algorithms can be improved from 44% to 72% and from 61% to 69%, respectively, by using the proposed optimization strategy.

关键词： march test algorithm Memory BIST Memory Fault Models Random Access Memory Memory Fault Detection Optimization

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Efficient march test algorithm for 1T1R cross-bar with complete fault coverage

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ELECTRONICS LETTERS 2016年第18期52卷 1520-1521页

作者： Liu, Peng You, Zhiqiang Kuang, Jishun Hu, Zhipeng Duan, Heng Wang, Weizheng Hunan Univ Coll Comp Sci & Elect Engn Key Lab Embedded & Network Comp Hunan Prov Changsha 410082 Hunan Peoples R China Hunan Inst Technol Coll Elect & Informat Engn Changsha Hunan Peoples R China Changsha Univ Sci & Technol Coll Comp & Commun Engn Changsha Hunan Peoples R China

As an attractive option of future non-volatile memories, resistive RAM (RRAM) has attracted more attentions. Among RRAM architectures, one transistor one memristor (1T1R) cross-bar is the most fledged one. A march C*-1T1R algorithm is proposed for 1T1R cross-bar. The pass-fail fault dictionary of the proposed march test algorithm is analysed. Analytical results show that the proposed test algorithm can detect all the modelled faults caused by the parametric variation of memristors, transistors and their interconnecting wires with a little test time overhead compared with previous methods.

关键词： resistive RAM wires (electric) integrated circuit testing memristor circuits memristors march test algorithm 1T1R cross-bar fault coverage nonvolatile memories resistive random access memory RRAM one transistor one memristor cross-bar pass-fail fault dictionary wire interconnection test time overhead

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Low Power march Memory test algorithm for Static Random Access Memories

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INTERNATIONAL JOURNAL OF ENGINEERING 2018年第2期31卷 292-298页

作者： Kumar, G. Rajesh Babulu, K. JNTUK Dept Elect & Commun Engn Kakinada India

Memories are most important building blocks in many digital systems. As the integrated circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many memory built in self-test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes more amount of power. test circuitry is intensively used for memory testing. This may cause excessive power consumption during memory testing. Sophisticated and efficient techniques with less overhead on power must be needed. Regarding memories, power consumption is very much high during testing when compared with normal functional mode. march test algorithms are popular testing techniques used for memory testing. Power consumption during testing can be reduced by reducing the switching activity in test circuitry. A new test technique is proposed in this paper to reduce power consumption in test mode by reducing the switching activity in Built in Self-test circuitry. Address sequencing in the address decoder is changed in such a way that it reduces switching activity.

关键词： Built in Self-test Low Power test march test algorithm Memory Built in Self-test Memory testing

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Generation of New Low-Complexity march algorithms for Optimum Faults Detection in SRAM

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2023年第8期42卷 2738-2751页

作者： Jidin, Aiman Zakwan Hussin, Razaidi Fook, Lee Weng Mispan, Mohd Syafiq Zakaria, Nor Azura Ying, Loh Wan Zamin, Norshuhani Univ Malaysia Perlis Fac Elect Engn & Technol Arau 02600 Malaysia Univ Tekn Malaysia Melaka Fak Teknol Kejuruteraan Elekt & Elekt Durian Tunggal 76100 Malaysia Emerald Syst Design Ctr IC Design Dept George Town 11900 Malaysia UST Global Malaysia UST Semicond Dept George Town 10200 Malaysia Saudi Elect Univ Coll Comp & Informat Riyadh 13316 Saudi Arabia

Memory BIST implements march test techniques extensively for testing embedded memories on a chip. A high-complexity test algorithm like the march MSS (18N) can guarantee the detection of all unlinked static faults in SRAM. In contrast, march algorithms with lower complexity can be used to reduce test costs and chip area overhead. Still, they have poor coverage of faults identified in the nanometer process technologies. Subsequently, a balance between the fault coverage (FC) and the test cost is necessary. This article presents a method to generate new march algorithms that provide optimum coverage on faults introduced by the nanometer process technologies. It was achieved by developing automated software to generate the new Data Background sequence and rearrange the existing march algorithms' test operations to remove redundancies and enable the sensitization and detection of the intended faults while preserving their complexities. Comprehensive fault detection analyses were conducted to assess their FCs and to find any removable redundant test operations. The proposed method produced new march AZ1 and march AZ2 algorithms, with 13N and 14N complexity, respectively, that provide optimum coverage of the targeted faults. They were successfully implemented in the Memory BIST controllers, and their functionalities were validated via simulations.

关键词： march test algorithm memory BIST memory fault detection memory fault models random access memory

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Novel march WY Approach for Dynamic Fault Detection in Memory BIST 16

Novel March WY Approach for Dynamic Fault Detection in Memor...

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16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)

作者： Loh, Wan Ying Hussin, Razaidi Ahmad, Norhawati Lee, Weng Fook Jidin, Aiman Zakwan Zakaria, Nor Azura Univ Malaysia Perlis Fac Elect Engn Technol Arau Malaysia Emerald Syst Design Ctr George Town Malaysia Univ Teknikal Malaysia Melaka Fac Teknol Kejuruteraan Elekt & Elekt Durian Tunggal Malaysia UST Global Sdn Bhd Semicond Dept Bayan Lepas Malaysia

ISBN: (纸本)9798350393613

Dynamic fault detection has shown an increasingly important role in the DPM level for embedded memories in SoC. Memory testing is directly related to the reliability of the whole SoC since embedded memories occupy a large area in the SoC and are used to store data for application usage. However, it is essential to bring down the test complexity of the march-based test algorithm for dynamic fault detection to maintain the test time and expenses within an acceptable economic range. march WY1 (66n) is proposed as the minimal march algorithm targeting unlinked two-operation single-cell dynamic faults and double-cell faults of types Sw and Saa to enhance the test efficiency for dynamic fault detection in SRAM. The proposed march WY1 (66n) has reduced test complexity by 4n compared to the well-known march MD2 (70n) while maintaining the same 100% dynamic fault coverages.

关键词： march test algorithm Dynamic Faults Memory BIST Minimal march algorithm Faults Detection

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MBIST Controller Based on march-ee algorithm

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2021年第9期30卷

作者： Ahmed, Mohammed Altaf Abuagoub, Ali Ma Prince Sattam bin Abdulaziz Univ Coll Comp Engn & Sci Dept Comp Engn Al Kharj Saudi Arabia

In the modern System on Chip (SoC)-based designs, embedded memory occupies the majority of the area. Therefore, the demand for fast self-testing plays a vital role in the SoC device as its memory density increases. The focus of this research study is to provide a self-testing mechanism integrated with the SoC design for fault diagnosis and failure analysis. In particular, this paper proposes a controller design to test memories at SoC devices, called a memory built-in self-test (MBIST) controller. This controller works on the principle of the proposed march-ee (enhanced elements) algorithm with the primary objective to improve the test speed, fault coverage, and power consumption at a low area overhead. The complete design of the MBIST controller with the associated march-ee algorithm is minimal and easy to be integrated into any SoC device to provide a vibrant feature of memory fault detection. The results obtained are compared with that provided by the existing march algorithms, using the same design specifications, where the proposed march-ee MBIST controller has shown better results in terms of power consumption, fault coverage, timing, and area.

关键词： System on chip (SoC) memory built-in-self-test (MBIST) march test algorithm embedded memory faults

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Fault Tolerant Improvement Mechanism for 3D Memories Using Built-In Self Repair Scheme

Fault Tolerant Improvement Mechanism for 3D Memories Using B...

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IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)

作者： Sivakumar, P. Karthy, G. Bharani, K. Vidya Kalasalingam Univ Elect & Commun Engn Dept Virudunagar 626126 Tamil Nadu India

ISBN: (纸本)9781509049967

An efficient BISR technique is proposed to find an optimum point of performance scheme is proposed for 2D and 3D memories. Fault Tolerant Improvement Mechanism is provided for all memories using Built-In Self-test (march test algorithm) which figure out the memory faults, total number of faults, and irreparability and test the memories simultaneously. Using LFSR architecture the transistor is reduced. After all memories are tested, only faulty memories are sequentially tested and the shared BIRA repaired the fault according to the sizes of memories in descending order to obtain the fast test and repair with low area overhead. Circuit design is created using LFSR architecture that reduces the flipflop level which leads to reduce the time. The detected faults are send to the BIST, then the BIST sends the faults to the BIRA module which uses Cresta for repair analysis and sends the solution. Three number of spare rows & columns are added along with 2 sub analyzers are used to accomplish a fast analysis speed, and an optimal repair rate for every different possible combinations of spare rows & columns.

关键词： 3D Memory march test algorithm BISR BIST RA CRESTA algorithm

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A snake addressing scheme for phase change memory testing

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Science China(Information Sciences) 2016年第10期59卷 222-232页

作者： Xiaole CUI Zuolin CHENG Chunglen LEE Xinnan LIN Yiqun WEI Xiaogang CHEN Zhitang SONG Key Laboratory of Integrated Microsystems Peking University Shenzhen Graduate School State Key Laboratory of Functional Materials for Informatics Shanghai Institute of Micro-System and Information Technology Chinese Academy of Sciences

Phase change memory(PCM) is one of the most promising candidates for next generation nonvolatile memory. However, PCM suffers from a variety of faults due to its special device structure and operation mechanism. A snake addressing scheme is introduced into the test algorithms of PCM to reduce the test time and excite proximity disturb faults more effectively. The march test algorithm with the proposed snake addressing scheme is less complex than most traditional test algorithms. In addition to conventional faults, it is capable of covering disturb and parasitic faults. Moreover, when incorporated with the sneak path testing method, it is able to test the read fault, read recovery fault, incomplete program fault 0, and false write fault.

关键词： phase change memory fault model snake addressing mode march test algorithm sneak path test method

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Generic BIST Architecture for testing of Content Addressable Memories

Generic BIST Architecture for Testing of Content Addressable...

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17th IEEE International On-Line testing Symposium (IOLTS)

作者： Grigoryan, H. Harutyunyan, G. Shoukourian, S. Vardanian, V. Zorian, Y. Synopsys France

ISBN: (纸本)9781457710551

Minimal march test algorithms are developed for single-port binary and ternary content addressable memories (CAMs). Based on these test algorithms a built-in-self-test (BIST) architecture for testing of CAMs is proposed. It is an extension of an existing BIST architecture for testing of static random access memories (SRAMs) and read-only memories (ROMs). This generic BIST architecture additionally supports the following important CAM specific features: power buffer-zones, multi-cycle compare operations, half/quarter words and walking patterns.

关键词： CAM BCAM TCAM BIST architecture fault march test algorithm

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