We consider high-rate systematic recursive convolutional encoders to be adopted as constituent encoders in turbo schemes. It has been shown by Douillard and Berrou that the construction of high-rate turbo codes by mea...
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ISBN:
(纸本)9781457705953
We consider high-rate systematic recursive convolutional encoders to be adopted as constituent encoders in turbo schemes. It has been shown by Douillard and Berrou that the construction of high-rate turbo codes by means of high-rate constituent encoders offers several advantages over the typical construction based on the puncturing of rate-1/2 constituent encoders. To reduce the decoding complexity associated with high-rate codes, we adopt the "minimal" trellis representation of convolutional codes introduced by McEliece and Lin. While in the literature this trellis has been obtained for nonrecursive nonsystematic generator matrices, we herein introduce the construction of the "minimal" trellis for a systematic recursive convolutional encoding matrix. We also derive expressions for the arithmetic decoding complexity when the max-log-map algorithm is applied over the conventional and the "minimal" trellises. Examples are provided, which show that significant savings in decoding complexity are obtained, while keeping the same error performance of conventional schemes, when the minimal trellis is used. Finally, a code search is conducted and examples are provided which indicate that a refinement in terms of decoding complexity-error performance trade-off is obtained.
This work addresses the problem of joint source-channel decoding of a Markov sequence which is first encoded by a source code, then encoded by a convolutional code, and sent through a noisy memoryless channel. It is s...
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This work addresses the problem of joint source-channel decoding of a Markov sequence which is first encoded by a source code, then encoded by a convolutional code, and sent through a noisy memoryless channel. It is shown that for Markov sources satisfying the so-called Monge property, both the maximum a posteriori probability (map) sequence decoding, as well as the soft output max-log-map decoding can be accelerated by a factor of K without compromising the optimality, where K is the size of the Markov source alphabet. The key to achieve a higher decoding speed is a convenient organization of computations at the decoder combined with a fast matrix search technique enabled by the Monge property. The same decrease in complexity follows, as a by-product of the development, for the soft output max-log-map joint source channel decoding in the case when the convolutional coder is absent, result which was not known previously.
This paper focuses on implementing an efficient and simplified turbo decoder with FPGA. The max-log-map algorithm is employed and a simplified and improved max-log-map algorithm is present. By carefully manipulating h...
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ISBN:
(纸本)9781424421077
This paper focuses on implementing an efficient and simplified turbo decoder with FPGA. The max-log-map algorithm is employed and a simplified and improved max-log-map algorithm is present. By carefully manipulating hardware, we implement the whole turbo decoder with a single-RSC structure. Comparing with the conventional decoder, our turbo decoder reduces about 60% hardware cost and operates up to 2Mbit/s. Finally, we investigate the performance of our FPGA-based turbo decoder in a FH-SS system with partial band jamming. The results drawn from this code are compared with a RS code. Results show that the turbo code significantly outperforms the RS code.
In the advent of very high data rates of the upcoming 3G long-term evolution telecommunication systems, there is a crucial need for efficient and flexible turbo decoder implementations. In this study, a max-log-map tu...
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In the advent of very high data rates of the upcoming 3G long-term evolution telecommunication systems, there is a crucial need for efficient and flexible turbo decoder implementations. In this study, a max-log-map turbo decoder is implemented as an application-specific instruction-set processor. The processor is accompanied with accelerating computing units, which can be controlled in detail. With a novel memory interface, the dual-port memory for extrinsic information is avoided. As a result, processing one trellis stage with max-log-map algorithm takes only 1.02 clock cycles on average, which is comparable to pure hardware decoders. With six turbo iterations and 277MHz clock frequency 22.7Mbps decoding speed is achieved on 130nm technology. Copyright (C) 2008 Perttu Salmela et al.
This paper proposes a modified iterative scheme(MI) for the data transmitted by more efficient way over inter-symbol interference(ISI) channels,then compares and analyzes the performance for three equalization algorit...
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This paper proposes a modified iterative scheme(MI) for the data transmitted by more efficient way over inter-symbol interference(ISI) channels,then compares and analyzes the performance for three equalization algorithms in MI: improved max-log-map(I-MLM) algorithm,maximum a posteriori(map) algorithm and linear minimum meansquared error(LMMSE) *** we analyze and compare these three algorithms in traditional turbo equalization(TE) ***,according to the good understanding of the aforementioned algorithms and the novel iterative(NI) scheme which combines parallel with serial concatenation turbo-like scheme,we propose the MI scheme and compare the performance of three algorithms in MI, named as MI-I-MLM,MI-map and MI-LMMSE *** analytical and simulation results demonstrate that the performance of MI-I-MLM is very close to MI-map and much better than MI-LMMSE while its computational complexity is much lower.
In the field of mobile communications, the energy issue of a turbo decoder becomes an equivalent constraint as throughput and performance. This paper describes a technique to reduce the internal bitwidth of the state ...
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ISBN:
(纸本)9781424412211
In the field of mobile communications, the energy issue of a turbo decoder becomes an equivalent constraint as throughput and performance. This paper describes a technique to reduce the internal bitwidth of the state metrics, and hence, to decrease the entire energy dissipation of a turbo decoder. This approach is based on the saturation of the state metrics. Two cases are investigated: saturation outside the ACS recursion loop and saturation inside the ACS recursion loop. The targeted system is the Universal Mobile Telecommunications System (UTMTS) with an 8-state turbo decoder using the max-log-map algorithm. When received symbols and extrinsic informations are respectively 4-bit and 6-bit quantized, the internal bitwidth of the state metrics can be reduced from 7 bits downto 4 bits. This reduction is paid by a loss of 0.1 dB at a Bit Error Rate (BER) of 10(-6). In addition, when 4 SISO decoders perform in parallel, the proposed optimization yields to a reduction of memory area by 10% and leads to an energy reduction of 24% for a 70 mn technology.
As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper presents an efficient reverse calculati...
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As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper presents an efficient reverse calculation method to lower the power consumption by reducing the number of memory accesses required in turbo decoding. The reverse calculation method is proposed for the max-log-map algorithm, and it is combined with a scaling technique to achieve a new decoding algorithm, called hybrid log-map, that results in a similar BER performance to the log-mapalgorithm. For the W-CDMA standard, experimental results show that 80% of memory accesses are reduced through the proposed reverse calculation method. A hybrid log-map turbo decoder based on the proposed reverse calculation reduces power consumption and memory size by 34.4% and 39.2%, respectively.
This paper proposes a low-complexity design for BCJR or maximum a posteriori (map) decoders. max-log-map algorithm, which offers a good compromise between performance and complexity, is selected for implementation. Th...
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ISBN:
(纸本)0780391527
This paper proposes a low-complexity design for BCJR or maximum a posteriori (map) decoders. max-log-map algorithm, which offers a good compromise between performance and complexity, is selected for implementation. The decoder architecture is parallel and pipeline. New quantization and new branch metric calculation unit are proposed in this paper. Overall decoder design is flexible to the transmission block lengths, which makes it appropriate for variable length transmission systems. Performance results are tested on turbo decoders and show that the proposed BUR decoder is quite suitable for turbo decoders. The chip is implemented in a 0.18-mu m six-layer metal CMOS technology and has the core size of 1mm(2) (including two memories). The throughput of the turbo decoder is 6.5Mb/s after 10 iterations.
A parallelised max-log-map model (P-max-log-map) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed mo...
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A parallelised max-log-map model (P-max-log-map) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-log-map algorithm;and therefore facilitates easy implementation.
作者：
Park, GHYoon, SHHong, DKang, CEYonsei Univ
Dept Elect & Comp Engn Informat & Telecommun Lab Seodaemoon Gu Seoul 120749 South Korea LG Elect Inc
LG R&D Complex 533 Mobile Comm Res Lab Dept Mobile Comm TechDongan Gu Kyeongku Do 431749 South Korea
Several implementation methods for a map decoder are proposed in this paper, Using a novel pipeline structured time-shared process, the authors are able to efficiently overcome the restrictions imposed by the recursio...
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Several implementation methods for a map decoder are proposed in this paper, Using a novel pipeline structured time-shared process, the authors are able to efficiently overcome the restrictions imposed by the recursion process on state metrics. and the complexity of the map decoder can be reduced to a level on the order of a SOVA (Soft Output Viterbi algorithm) decoder. In addition. the authors propose an efficient controller structure that can be used for variable frame-size systems such as cdma-2000. The map decoder using a block-wise algorithm designed here was implemented in only one 20,000 gate circuit. It was validated by VHDL, which was compared with the results of the initial simulation (C programs). The decoder demonstrated a 300 kbps decoding processing ability with 8 iterations on a FPGA circuit, with a deviation only about 0.1-0.2 dB greater than that for an ideal map decoder, even when all hardware environments are considered.
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