Design and implementation of a Turbo decoder on FPGA is a challenging task. Various algorithms based on the BCJR algorithm have been proposed to enable the implementation of Turbo decoding in a hardware device. With t...
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ISBN:
(纸本)9781467365406
Design and implementation of a Turbo decoder on FPGA is a challenging task. Various algorithms based on the BCJR algorithm have been proposed to enable the implementation of Turbo decoding in a hardware device. With the advent of FPGAs, the realization of the BCJR algorithm and different simplified versions of BCJR algorithm on hardware is possible. A VHDL implementation of Turbo decoder using the max-log-map algorithm has been discussed in this paper. The target device used for this implementation is Xilinx Virtex-6 FPGA. Simulation and synthesis were carried out using ModelSim SE 6.1 and Xilinx ISE 10.1. BER plots and input and output waveforms for interleaver, deinterleaver, max-log-map decoder and Turbo decoder are also presented.
Probabilistic constellation shaping (PCS) improves the spectral efficiency by adjusting the probability distribution of the transmitted symbols to match the channel characteristics. The conventional log-maximum A Post...
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ISBN:
(纸本)9798350304060;9798350304053
Probabilistic constellation shaping (PCS) improves the spectral efficiency by adjusting the probability distribution of the transmitted symbols to match the channel characteristics. The conventional log-maximum A Posteriori (log-map) algorithm can work for demodulation of PCS system by taking into account the probability of each constellation point. However, the conventional max-log-map algorithm cannot be applied directly. In this paper, a simplified soft-demapping scheme is proposed based on the max-log-map algorithm for the PCS system. The proposed scheme has a lower complexity than the logmapalgorithm with acceptable performance loss. In addition, the distribution mismatch between transmitter and receiver is evaluated. The results show that four distributions are adequate for PCS-64 and PCS-256 to cover a wide range of signal-to-noise ratios.
This paper presents a novel model-driven deep learning (DL) architecture, called TurboNet, for turbo decoding that integrates DL into the traditional max-log-maximum a posteriori (map) algorithm. The TurboNet inherits...
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This paper presents a novel model-driven deep learning (DL) architecture, called TurboNet, for turbo decoding that integrates DL into the traditional max-log-maximum a posteriori (map) algorithm. The TurboNet inherits the superiority of the max-log-map algorithm and DL tools and thus presents excellent error-correction capability with low training cost. To design the TurboNet, the original iterative structure is unfolded as deep neural network (DNN) decoding units, where trainable weights are introduced to the max-log-map algorithm and optimized through supervised learning. To efficiently train the TurboNet, a loss function is carefully designed to prevent tricky gradient vanishing issue. To further reduce the computational complexity and training cost of the TurboNet, we can prune it into TurboNet+. Compared with the existing black-box DL approaches, the TurboNet+ has considerable advantage in computational complexity and is conducive to significantly reducing the decoding overhead. Furthermore, we also present a simple training strategy to address the overfitting issue, which enable efficient training of the proposed TurboNet+. Simulation results demonstrate TurboNet+'s superiority in error-correction ability, signal-to-noise ratio generalization, and computational overhead. In addition, an experimental system is established for an over-the-air (OTA) test with the help of a 5G rapid prototyping system and demonstrates TurboNet's strong learning ability and great robustness to various scenarios.
The rapid growth in wireless communication has caused an increased demand for high speed error control decoders with improved BER performance. Turbo codes, the Shannon limit approaching codes, use max-log-map decoders...
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ISBN:
(纸本)9781538646922
The rapid growth in wireless communication has caused an increased demand for high speed error control decoders with improved BER performance. Turbo codes, the Shannon limit approaching codes, use max-log-map decoders as the component decoders in the iterative decoding process. The demand for high speed error control decoders has led to an increased interest in the design of hardware-secure max-log-map decoders with high throughput and reduced area. This paper focuses on designing a high throughput max-log-map decoder with reduced area and analyzing the effect of a run time triggered multinet connected Trojan on its performance. High throughput is achieved by using radix-4 and radix-8 architectures and area is optimized using maximum sharing of resources (MSR) architec-ture. This architecture uses a modified add-compare-select unit designed by effectively utilizing the relationship existing between the branch metrics. Trojan analysis is performed by inserting a run time triggered multinet connected Trojan and comparing its performance with the Trojan free decoder.
In the implementation of turbo-like decoder, the size of state metrics cache (SMC) has a predominant impact on the core area and the overall power dissipation. Different from previous reported decoding schemes, in the...
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In the implementation of turbo-like decoder, the size of state metrics cache (SMC) has a predominant impact on the core area and the overall power dissipation. Different from previous reported decoding schemes, in the proposed decoding schemes, a compressing module and a regeneration module are added to the decoder. The compressing module sorts the forward state metrics from the minimum to the maximum, by which an index sequence and the corresponding increase metrics are calculated, and subsequently are stored in the SMC. In the regeneration module, the forward state metrics are estimated with the index sequence and the increase metrics that accessed from the SMC. With the cost of dummy calculation that is performed by the compressing and the regeneration modules, two decoding schemes are proposed. For an eight-state turbo codes, the linear and the nonlinear estimation based decoding schemes reduce the SMC size by 62.5% and 57.5%, respectively. The bit error rate (BER) simulation is performed for both binary turbo code and duo binary convolutional turbo code, and shows BER of the linear estimation-based scheme is superior to that of the enhanced max-log-map (the maximum a posteriori probability) algorithm, whereas BER of the non-linear estimation-based decoding scheme is very close to that of the near optimal decoding scheme.
In the paper, a new implementation of a 3GPP LTE standards compliant turbo decoder based on GPGPU is proposed. It uses the newest GPU-Tesla K20c, which is based on the Kepler GK110 architecture. The new architecture h...
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ISBN:
(纸本)9781479944163
In the paper, a new implementation of a 3GPP LTE standards compliant turbo decoder based on GPGPU is proposed. It uses the newest GPU-Tesla K20c, which is based on the Kepler GK110 architecture. The new architecture has more powerful parallel computing capability and we use it to fully exploit the parallelism in the turbo decoding algorithm in novel ways. Meanwhile, we use various memory hierarchies to meet various kinds of data demands on speed and capacity. Simulation shows that our implementation is practical and it gets 76% improvement on throughput over the latest GPU implementation. The result demonstrates that the newest Kepler architecture is suitable for turbo decoding and it can be a promising reconfigurable platform for the communication system.
In this paper, the performance of the Least Squares (LS) estimator along with turbo codes in OFDM is evaluated for the SUI channel models in the presence of AWGN. Turbo codes are used in this paper because of its BER ...
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ISBN:
(纸本)9781479925810
In this paper, the performance of the Least Squares (LS) estimator along with turbo codes in OFDM is evaluated for the SUI channel models in the presence of AWGN. Turbo codes are used in this paper because of its BER performance close to Shannon limit. The iterative turbo decoder exchanges soft information between the component decoders. maximum A Posteriori (map) and its simplified version max-log-map algorithms are used for the component decoders. The performance and complexity comparison is also made between the decoding algorithms. Moreover the effect of memory order on the performance of the decoding algorithms is also studied.
The iterative decoding in turbo code has very high decoding complexity. This paper adopts the improved log-mapalgorithm for decoding of Space-Time Turbo Trellis Code (ST-Turbo TC) in the slow Rayleigh fading channels...
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The iterative decoding in turbo code has very high decoding complexity. This paper adopts the improved log-mapalgorithm for decoding of Space-Time Turbo Trellis Code (ST-Turbo TC) in the slow Rayleigh fading channels. Using the MacLaurin formulae, the proposed algorithm expands the logarithmic function of the log-map. It makes the computation much easier and the operation of the hardware system much faster. Simulation results show that the proposed algorithm performs very closely to the log-mapalgorithm for decoding of ST-Turbo TC in slow Rayleigh fading channels.
In the field of mobile communication systems, the energy issue of a turbo decoder becomes an equivalent constraint as throughput and performance. This paper presents a contribution to the reduction of the power consum...
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In the field of mobile communication systems, the energy issue of a turbo decoder becomes an equivalent constraint as throughput and performance. This paper presents a contribution to the reduction of the power consumption in the turbo decoder. The main idea is based on re-encoding technique combined with dummy insertion during the iterative decoding process. This technique, named "toward zero path" (TZP) helps in reducing the state transition activity of the max-log-map algorithm by trying to maintain the survivor path on the 'zero path' of the trellis. The design of a turbo decoder based on the TZP technique, associated with different power reduction technique (saturation of state metrics, stoping criterium) is described. The resulting turbo decoder was implemented onto a Xilinx VirtexII-Pro field-programmable gate array (FPGA) in a digital communication experimental setup. Performance and accurate power dissipation measurements have been done thanks to dynamic partial reconfiguration of the FPGA device. The experimental results have shown the interest of the different contributions for the design of turbo decoders.
This paper proposes an improved max-log-maximum a posteriori (map) algorithm for turbo decoding and turbo equalization. The proposed algorithm utilizes the MacLaurin Series to expand the logarithmic term in the Jacobi...
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This paper proposes an improved max-log-maximum a posteriori (map) algorithm for turbo decoding and turbo equalization. The proposed algorithm utilizes the MacLaurin Series to expand the logarithmic term in the Jacobian logarithmic function of the log-mapalgorithm. In terms of complexity, the proposed algorithm can easily be implemented by means of adders and comparators as this is the case for the max-log-map algorithm. In addition, simulation results show that the proposed algorithm performs very closely to the log-mapalgorithm for both turbo decoding over additive-white-Gaussian-noise channels and turbo equalization over frequency-selective channels. Further, it is shown than even in a high-loss intersymbol-interference channel, the proposed algorithm preserves its performance close to that of the log-mapalgorithm, while there is a wide gap between the performance of the log-map and max-log-map turbo equalizers.
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