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检索条件"主题词=Memory Access Patterns"

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Classifying memory access patterns for Prefetching 20

Classifying Memory Access Patterns for Prefetching

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25th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

作者： Ayers, Grant Litz, Heiner Kozyrakis, Christos Ranganathan, Parthasarathy Stanford Univ Stanford CA 94305 USA UC Santa Cruz Santa Cruz CA USA Google Mountain View CA 94043 USA

ISBN: (纸本)9781450371025

Prefetching is a well-studied technique for addressing the memory access stall time of contemporary microprocessors. However, despite a large body of related work, the memory access behavior of applications is not well understood, and it remains difficult to predict whether a particular application will benefit from a given prefetcher technique. In this work we propose a novel methodology to classify the memory access patterns of applications, enabling well-informed reasoning about the applicability of a certain prefetcher. Our approach leverages instruction dataflow information to uncover a wide range of access patterns, including arbitrary combinations of offsets and indirection. These combinations- or prefetch kernels-represent reuse, strides, reference locality, and complex address generation. By determining the complexity and frequency of these access patterns, we enable reasoning about prefetcher timeliness and criticality, exposing the limitations of existing prefetchers today. Moreover, using these kernels, we are able to compute the next address for the majority of top-missing instructions, and we propose a software prefetch injection methodology that is able to outperform state-of-the-art hardware prefetchers.

关键词： prefetcher memory access patterns wsc warehouse-scale computers prefetching dataflow classification

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Detection of Previously Unseen Malware using memory access patterns Recorded Before the Entry Point 8

Detection of Previously Unseen Malware using Memory Access P...

引用

8th IEEE International Conference on Big Data (Big Data)

作者： Banin, Sergii Dyrkolbotn, Geir Olav Norwegian Univ Sci & Technol Dept Informat Secur & Commun Technol Trondheim Norway

ISBN: (纸本)9781728162515

Recently it has been shown, that it is possible to detect malware based on the memory access patterns produced before executions reaches its Entry Point. In this paper, we investigate the usefulness of memory access patterns over time, i.e to what extent can machine learning algorithm trained on "old" data, detect new malware samples, that was not part of the training set and how does this performance change over time. During our experiments, we found that machine learning models trained on memory access patterns of older samples can provide both high accuracy and a high true positive rate for the period from several months to almost a year from the update of the model. We also perform a substantial analysis of our findings that may aid researchers who work with malware and Big Data.

关键词： information security malware detection low-level features memory access patterns

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Understanding the Impact of memory access patterns in Intel Processors

Understanding the Impact of Memory Access Patterns in Intel ...

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IEEE/ACM Workshop on memory Centric High Performance Computing (MCHPC)

作者： Monil, Mohammad Alaul Haque Lee, Seyong Vetter, Jeffrey S. Malony, Allen D. Univ Oregon Eugene OR 97403 USA Oak Ridge Natl Lab Oak Ridge TN USA

ISBN: (纸本)9780738110660

Because of increasing complexity in the memory hierarchy, predicting the performance of a given application in a given processor is becoming more difficult. The problem is worsened by the fact that the hardware needed to deal with more complex memory traffic also affects energy consumption. Moreover, in a heterogeneous system with shared main memory, the memory traffic between the last level cache (LLC) and the memory creates contention between other processors and accelerator devices. For these reasons, it is important to investigate and understand the impact of different memory access patterns on the memory system. This study investigates the interplay between Intel processors' memory hierarchy and different memory access patterns in applications. The authors explore sequential streaming and strided memory access patterns with the objective of predicting LLC-dynamic random access memory (DRAM) traffic for a given application in given Intel architectures. Moreover, the impact of prefetching is also investigated in this study. Experiments with different Intel micro-architectures uncover mechanisms to predict LLC-DRAM traffic that can yield up to 99% accuracy for sequential streaming access patterns and up to 95% accuracy for strided access patterns.

关键词： Intel Broadwell Sky Lake Cascade Lake memory access patterns memory traffic prediction

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On the Detectability of Control Flow Using memory access patterns 3

On the Detectability of Control Flow Using Memory Access Pat...

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3rd Workshop on System Software for Trusted Execution (SysTEX)

作者： Buhren, Robert Hetzelt, Felicitas Pirnay, Niklas TU Berlin SecT Berlin Germany TU Berlin Berlin Germany

ISBN: (纸本)9781450359986

Shielding systems such as AMD's Secure Encrypted Virtualization aim to protect a virtual machine from a higher privileged entity such as the hypervisor. A cornerstone of these systems is the ability to protect the memory from unauthorized accesses. Despite this protection mechanism, previous attacks leveraged the control over memory resources to infer control flow of applications running in a shielded system. While previous works focused on a specific target application, there has been no general analysis on how the control flow of a protected application can be inferred. This paper tries to overcome this gap by providing a detailed analysis on the detectability of control flow using memory access patterns. To that end, we do not focus on a specific shielding system or a specific target application, but present a framework which can be applied to different types of shielding systems as well as to different types of attackers. By training a random forest classifier on the memory accesses emitted by syscalls of a shielded entity, we show that it is possible to infer the control flow of shielded entities with a high degree of accuracy.

关键词： Shielding Systems memory access patterns Side-Channels Secure Encrypted Virtualization

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memory access patterns: The Missing Piece of the Multi-GPU Puzzle 15

Memory Access Patterns: The Missing Piece of the Multi-GPU P...

引用

International Conference for High Performance Computing, Networking, Storage and Analysis (SC)

作者： Ben-Nun, Tal Levy, Ely Barak, Amnon Rubin, Eri Hebrew Univ Jerusalem Dept Comp Sci IL-91905 Jerusalem Israel

ISBN: (纸本)9781450337236

With the increased popularity of multi-GPU nodes in modern HPC clusters, it is imperative to develop matching programming paradigms for their efficient utilization. In order to take advantage of the local GPUs and the low-latency high-throughput interconnects that link them, programmers need to meticulously adapt parallel applications with respect to load balancing, boundary conditions and device synchronization. This paper presents MAPS-Multi, an automatic multi-GPU partitioning framework that distributes the workload based on the underlying memory access patterns. The framework consists of host-and device-level APIs that allow programs to efficiently run on a variety of GPU and multi-GPU architectures. The framework implements several layers of code optimization, device abstraction, and automatic inference of inter-GPU memory exchanges. The paper demonstrates that the performance of MAPS-Multi achieves near-linear scaling on fundamental computational operations, as well as real-world applications in deep learning and multivariate analysis.

关键词： Multi-GPU Programming memory access patterns

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MEGA: More Efficient Graph Attention for GNNs 44

MEGA: More Efficient Graph Attention for GNNs

引用

44th IEEE International Conference on Distributed Computing Systems (ICDCS)

作者： Deng, Weishu Rao, Jia Univ Texas Arlington Dept Comp Sci & Engn Arlington TX 76019 USA

ISBN: (纸本)9798350386066;9798350386059

Graph neural networks (GNNs) have demonstrated effectiveness across diverse application domains by leveraging graph information to uncover intrinsic correlations alongside feature representation. This enables GNNs to explore richer information compared to conventional neural networks, resulting in enhanced predictive performance. However, the integration of graph-structured data into the learning process poses two challenges. First, the sparsity and irregularity of the graph representation result in inefficient and expensive memory accesses on throughput-oriented accelerators, such as GPUs. Second, as GNN training involves interleaved graph operations to extract topological information and neural operations to update node or edge embeddings, the joint optimization of these two operations on accelerators is challenging due to their distinct resource requirements. Among GNN graph operations, graph attention which helps focus GNN training on highly correlated nodes is critical to training performance and model accuracy. However, our profiling of representative GNNs reveals that irregular memory access during graph attention accounts for the dominating overhead in GNN training. To address this issue, this paper proposes a more efficient graph attention method MEGA to accelerate GNN training. MEGA converts the original graph representation into one that regularizes memory access patterns for graph attention. Specifically, during preprocessing, MEGA traverses a graph to derive a schedule for graph attention and uses the schedule to reorganize the graph representation for optimized memory access. MEGA explores several techniques to balance memory access efficiency and preserve the original graph properties to avoid the loss of model accuracy. Experimental results with representative GNNs and graph data sets show that MEGA consistently outperforms conventional graph attention methods with up to 3x speedup.

关键词： Graph Neural Networks GPU Computing memory access patterns Data transaction

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MemFriend: Understanding memory Performance with Spatial-Temporal Affinity 24

MemFriend: Understanding Memory Performance with Spatial-Tem...

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10th International Symposium on memory Systems

作者： Suriyakumar, Yasodha Tallent, Nathan R. Marquez, Andres Karavanic, Karen L. Kilic, Ozgur O. Portland State Univ Portland OR 97207 USA Pacific Northwest Natl Lab Richland WA 99352 USA Brookhaven Natl Lab Upton NY 11973 USA

ISBN: (纸本)9798400710919

In HPC applications, memory access behavior is one of the main factors affecting performance. Improving an application's memory access behavior requires studying spatial-temporal data locality. Existing data locality analyses focus on single locations. We introduce locality metrics between pairs of memory locations that quantify three dimensions of spatial-temporal affinity: temporal access proximity, forward access correlation, and nearby access correlation. We describe methods for distinguishing between potential vs. realized affinity and for reasoning about affinity (or friendship) at multiple resolutions (4D, 3D, 2D, 1D). Finally, we construct spatial-temporal affinity signatures that classify memory behavior and are used to reason about changes in software (data relayout, code refactoring) or hardware (caching, prefetching). We describe methods for signature visualization, interpretation, and quantitative comparison of signatures. We evaluate our methodology using applications with variants that contrast data structures, data layouts and algorithms. We show that spatial-temporal affinity analysis provides novel insights and enables predictive reasoning about application performance.

关键词： Data locality spatial-temporal affinity memory access patterns affinity signature application performance

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SPARTA: Spatial Acceleration for Efficient and Scalable Horizontal Diffusion Weather Stencil Computation 23

SPARTA: Spatial Acceleration for Efficient and Scalable Hori...

引用

37th ACM International Conference on Supercomputing (ACM ICS)

作者： Singh, Gagandeep Khodamoradi, Alireza Denolf, Kristof Lo, Jack Gomez-Luna, Juan Melber, Joseph Bisca, Andra Corporaal, Henk Mutlu, Onur AMD Res Hyderabad Andhra Pradesh India Swiss Fed Inst Technol Zurich Switzerland Eindhoven Univ Technol Eindhoven Netherlands

ISBN: (纸本)9798400700569

Fast and accurate climate simulations and weather predictions are critical for understanding and preparing for the impact of climate change. Real-world climate and weather simulations involve the use of complex compound stencil kernels, which are composed of a combination of different stencils. Horizontal diffusion is one such important compound stencil found in many climate and weather prediction models. Its computation involves a large amount of data access and manipulation that leads to two main issues on current computing systems. First, such compound stencils have high memory bandwidth demands as they require large amounts of data access. Second, compound stencils have complex data access patterns and poor data locality, as the memory access pattern is typically irregular with low arithmetic intensity. As a result, state-of-the-art CPU and GPU implementations suffer from limited performance and high energy consumption. Recent works propose using FPGAs as an alternative to traditional CPU and GPU-based systems to accelerate weather stencil kernels. However, we observe that stencil computation cannot leverage the bit-level flexibility available on an FPGA because of its complex memory access patterns, leading to high hardware resource utilization and low peak performance. We introduce SPARTA, a novel spatial accelerator for horizontal diffusion weather stencil computation. We exploit the two-dimensional spatial architecture to efficiently accelerate the horizontal diffusion stencil by designing the first scaled-out spatial accelerator using the MLIR (Multi-Level Intermediate Representation) compiler framework. We evaluate SPARTA on a real cutting-edge AMD-Xilinx Versal AI Engine (AIE) spatial architecture. Our real-system evaluation results demonstrate that SPARTA outperforms state-of-the-art CPU, GPU, and FPGA implementations by 17.1x, 1.2x, and 2.1x, respectively. Compared to the most energy-efficient design on an HBM-based FPGA, SPARTA provides 2.43x higher en

关键词： spatial computing systems dataflow architectures high-performance computing hybrid systems weather prediction stencil computation memory access patterns climate modeling

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MemGaze: Rapid and Effective Load-Level memory Trace Analysis

MemGaze: Rapid and Effective Load-Level Memory Trace Analysi...

引用

IEEE International Conference on Cluster Computing (CLUSTER)

作者： Kilic, Ozgur O. Tallent, Nathan R. Suriyakumar, Yasodha Xie, Chenhao Marquez, Andres Eranian, Stephane Pacific Northwest Natl Lab Richland WA 99352 USA Portland State Univ Portland OR 97207 USA Google Inc Mountain View CA USA

ISBN: (数字)9781665498562

ISBN: (纸本)9781665498562

A challenge of memory trace analysis is combining detailed analysis and low overhead measurement. Currently, hardware/software-based analysis of load-level sequences easily incurs time slowdowns of 100x. We present MemGaze, a tool for low-overhead, high-resolution memory trace analysis. MemGaze uses Intel's Processor Tracing (PT) instruction ptwrite to collect sampled and compressed memory address traces for load-level, sequence-aware analysis of data reuse. We describe multiresolution analysis for locations vs. operations, accesses vs. spatiotemporal reuse, and reuse (distance, rate, volume) vs. access patterns. Both trace size and resolution are controllable. We use MemGaze to elucidate the memory effects of different data structures and algorithms. For sampled traces that are approximate to 1% of a full one, analysis metrics have 1-25% MAPE for histograms of varying dynamic sequence lengths. With current suboptimal kernel support (PT runs continuously), MemGaze's time overhead is typically 10-95%;7x at worst. However, when PT runs only during samples, overhead is 10-35% on memory intensive regions and correlates with executed ptwrites.

关键词： memory access tracing processor tracing spatio-temporal reuse footprint memory access patterns MemGaze

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Pinpointing the memory Behaviors of DNN Training

Pinpointing the Memory Behaviors of DNN Training

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IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

作者： Li, Jiansong Dong, Xiao Li, Guangli Zhao, Peng Wang, Xueying Chen, Xiaobing Yu, Xianzhi Yang, Yongxin Jiang, Zihan Cao, Wei Liu, Lei Feng, Xiaobing Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China Tencent Youtu Lab Shanghai Peoples R China Huawei Technol Co Ltd Beijing Peoples R China

ISBN: (纸本)9781728186436

The training of deep neural networks (DNNs) is usually memory-hungry due to the limited device memory capacity of DNN accelerators. Characterizing the memory behaviors of DNN training is critical to optimize the device memory pressures. In this work, we pinpoint the memory behaviors of each device memory block of GPU during training by instrumenting the memory allocators of the runtime system. Our results show that the memory access patterns of device memory blocks are stable and follow an iterative fashion. These observations are useful for the future optimization of memory-efficient training from the perspective of raw memory access patterns.

关键词： DNN Training memory access patterns Work-load Characterizing

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