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26th IEEE International Symposium on High Performance Computer Architecture (HPCA)

作者： Chen, Jian Zhang, Ying Jiang, Xiaowei Zhao, Li Cao, Zheng Liu, Qiang Alibaba Grp Alibaba Cloud Hangzhou Peoples R China

ISBN: (纸本)9781728161495

Workload tracing is the foundational technology that many applications hinge upon. However, recent paradigm shift toward cloud computing has caused tremendous challenges to traditional workload tracing. Existing solutions either require a dedicated offline cluster or fail to capture the full-spectrum workload characteristics. This paper proposes DWT, a novel framework that leverages fast online instruction tracing, and uses synthetic data offline for memory access pattern reconstruction, thereby capturing the full workload characteristics while obviating the need of dedicated clusters. Experiment results show that the stack distance profiles generated from synthetic address traces match well with the original ones across all SPEC CPU 2017 programs and representative cloud applications, with correlation coefficient R-2 no less than 0.9. The page-level access frequencies also match well with those of the original programs. This decoupled tracing approach not only removes the roadblocks on workload characterization for data centers, but also enables new applications such as efficient online resource management.

关键词： Datacenter workload tracing memory access patterns Performance modeling Synthetic data

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Poster: Ensemble Malware Analysis for Evaluating the Integrity of Mission Critical Devices Poster 12

Poster: Ensemble Malware Analysis for Evaluating the Integri...

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Conference on Security and Privacy inWireless and Mobile Networks (WiSec)

作者： Heras, Robert Perez-Pons, Alexander Florida Int Univ Dept Elect & Comp Engn Miami FL 33174 USA

ISBN: (纸本)9781450367264

The rapid evolution of technology in our sociality has brought great advantages, but at the same time it has increased the cybersecurity threats associated with a constantly expanded surface exposure. At the forefront of these threats is the proliferation of malware from traditional computing platforms to the rapidly expanding Internet-of-things. Our premise is that malware needs to be detected as soon as possible to prevent extensive consequence linked to the fulfillment of its malicious activity. Our proposed framework analyzes task structure features as well as the system calls and memory access patterns made by a process to determine its validity and integrity. The proposed scheme would use all three approaches applying an ensemble technique to detect malware.

关键词： Feature Extraction Task Structure Analysis System Calls memory access patterns Malware Analysis

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Designing and building application-centric parallel memories

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2020年第15期32卷 e5485-e5485页

作者： Stramondo, Giulio Ciobanu, Catalin Bogdan de Laat, Cees Varbanescu, Ana Lucia Univ Amsterdam Inst Informat Amsterdam Netherlands

memory bandwidth is a critical performance factor for many applications and architectures. Intuitively, a parallel memory could be a good solution for any bandwidth-limited application, yet building application-centric custom parallel memories remains a challenge. In this work, we present a comprehensive approach to tackle this challenge and demonstrate how to systematically design and implement application-centric parallel memories. Specifically, our approach (1) analyzes the application memory access traces to extract parallel accesses, (2) configures our parallel memory for maximum performance, and (3) builds the actual application-centric memory system. We further provide a simple performance prediction model for the constructed memory system. We evaluate our approach with two sets of experiments. First, we demonstrate how our parallel memories provide performance benefits for a broad range of memory access patterns. Second, we prove the feasibility of our approach and validate our performance model by implementing and benchmarking the designed parallel memories using FPGA hardware and a sparse version of the STREAM benchmark.

关键词： FPGA high-bandwidth parallel memories memory access patterns STREAM benchmark

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CaL: Extending Data Locality to Consider Concurrency for Performance Optimization

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IEEE TRANSACTIONS ON BIG DATA 2018年第2期4卷 273-288页

作者： Liu, Yuhang Sun, Xian-He Chinese Acad Sci State Key Lab Comp Architecture Inst Comp Technol 6 Kexueyuan South Rd Zhongguancun Beijing 100190 Peoples R China IIT Dept Comp Sci Chicago IL 60616 USA

Big data applications demand a better memory performance. Data Locality has been the focus of reducing data access delay. Data access concurrency, however, has become prevalent in modern memory systems in recent years. How to extend existing locality-based performance optimization to consider data concurrency becomes a timely issue facing the researchers and practitioners in the field of computing, especially in the field of big data computing. In this study, we introduce the concept and definition of Concurrency-aware data access Locality (CaL), which, as its name states, extends the concept of locality by considering concurrency. Compared to the conventional concept of locality, CaL accurately reflects the combined impact of data access locality and concurrency in modern memory systems and is very effective for data intensive applications. The value of CaL can be quantitatively measured directly by performance counters in mainstream commercial processors and is practically feasible. Two theoretical results are presented to reveal the relationships between CaL and existing memory system performance metrics of memory accesses per cycle (APC), average memory access time (AMAT), and memory bandwidth (B). In this way, we provide a methodology to use existing locality-based optimization methods directly or in combination with data concurrency optimizations, to improve the value of CaL and to improve the performance of a memory system. To demonstrate the practical value of CaL, we conduct four case studies to illustrate the power of concurrency-aware locality optimization. Compared with the conventional locality based optimization, the CaL-aware design has achieved significant performance improvement. It achieved a 3.12-fold speedup on K-means, which is a widely-used data analytic kernel from the big data benchmarks.

关键词： memory wall memory stall time memory concurrency memory hierarchy memory access patterns

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Data mining the memory access stream to detect anomalous application behavior 17

Data mining the memory access stream to detect anomalous app...

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14th ACM International Conference on Computing Frontiers

作者： Moreira, Francis B. Diener, Matthias Navaux, Philippe O. A. Koren, Israel Informat Inst UFRGS Porto Alegre RS Brazil Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

ISBN: (纸本)9781450344876

Detecting anomalous application executions is a challenging problem, due to the diversity of anomalies that can occur, such as programming bugs, silent data corruption, or even malicious code corruption. Moreover, the similarity to a regular execution that can occur in these cases, especially in silent data corruption, makes distinction from normal executions difficult. In this paper, we develop a mechanism that can detect such anomalous executions based on changes in the memory access pattern of an application. We analyze memory patterns using a two-level machine learning approach. First, we classify the behavior of different memory access periods within applications using Gaussian mixtures. Then, based on these classifications, we construct matrix representations of Markov chains to obtain information regarding the temporal behavior of these memory accesses. Based on metrics of matrix similarity, we can classify whether the application behaves as expected or anomalously. Using gradient boosting on the metrics of matrix similarity, our technique correctly classifies more than 85% of all executions, identifying instances of the same application and different applications. We can also detect a range of faulty executions caused by benign or malicious permanent bit flips in the code section.

关键词： memory access patterns machine learning single bit flips

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access Pattern-Aware Cache Management for Improving Data Utilization in GPU 17

Access Pattern-Aware Cache Management for Improving Data Uti...

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44th Annual International Symposium on Computer Architecture (ISCA)

作者： Koo, Gunjae Oh, Yunho Ro, Won Woo Annavaram, Murali Univ Southern Calif Los Angeles CA 90089 USA Yonsei Univ Seoul South Korea

ISBN: (纸本)9781450348928

Long latency of memory operation is a prominent performance bottleneck in graphics processing units (GPUs). The small data cache that must be shared across dozens of warps (a collection of threads) creates significant cache contention and premature data eviction. Prior works have recognized this problem and proposed warp throttling which reduces the number of active warps contending for cache space. In this paper we discover that individual load instructions in a warp exhibit four different types of data locality behavior: (1) data brought by a warp load instruction is used only once, which is classified as streaming data (2) data brought by a warp load is reused multiple times within the same warp, called intra-warp locality (3) data brought by a warp is reused multiple times but across different warps, called inter-warp locality (4) and some data exhibit both a mix of intra-and inter-warp locality. Furthermore, each load instruction exhibits consistently the same locality type across all warps within a GPU kernel. Based on this discovery we argue that cache management must be done using per-load locality type information, rather than applying warp-wide cache management policies. We propose access Pattern-aware Cache Management (APCM), which dynamically detects the locality type of each load instruction by monitoring the accesses from one exemplary warp. APCM then uses the detected locality type to selectively apply cache bypassing and cache pinning of data based on load locality characterization. Using an extensive set of simulations we show that APCM improves performance of GPUs by 34% for cache sensitive applications while saving 27% of energy consumption over baseline GPU.

关键词： GPGPU cache management memory access patterns

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An Instrumentation Approach for Hardware-Agnostic Software Characterization

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2016年第5期44卷 924-948页

作者： Anghel, Andreea Vasilescu, Laura Mihaela Mariani, Giovanni Jongerius, Rik Dittmann, Gero IBM Res Zurich Ruschlikon Switzerland Univ Politehn Bucuresti Bucharest Romania IBM Res Dwingeloo Netherlands

Simulators and empirical profiling data are often used to understand how suitable a specific hardware architecture is for an application. However, simulators can be slow, and empirical profiling-based methods can only provide insights about the existing hardware on which the applications are executed. While the insights obtained in this way are valuable, such methods cannot be used to evaluate a large number of system designs efficiently. Analytical performance evaluation models are fast alternatives, particularly well-suited for system design-space exploration. However, to be truly application-specific, they need to be combined with a workload model that captures relevant application characteristics. In this paper we introduce PISA, a framework based on the LLVM infrastructure that is able to generate such a model for sequential and parallel applications by performing hardware-independent characterization. Characteristics such as instruction-level parallelism, memory access patterns and branch behavior are analyzed per thread or process during application execution. To illustrate the potential of the framework, we provide a detailed characterization of a representative benchmark for graph-based analytics, Graph 500. Finally, we analyze how the properties extracted with PISA across Graph 500 and SPEC CPU2006 applications compare to measurements performed on x86 and POWER8 processors.

关键词： Workload characterization Hardware-agnostic Graph 500 Design-space exploration memory access patterns Instruction-level parallelism Branch entropy Hardware measurements

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Switchable cache: utilising dark silicon for application specific cache optimisations

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IET COMPUTERS AND DIGITAL TECHNIQUES 2016年第4期10卷 157-164页

作者： Nawinne, Isuru Javaid, Haris Ragel, Roshan Parameswaran, Sri Univ New S Wales Sch Comp Sci & Engn Sydney NSW Australia Google Inc Mountain View CA USA Univ Peradeniya Dept Comp Engn Peradeniya Sri Lanka

Caches are used to improve memory access time and energy consumption. The cache configuration which enables the best performance often differs between applications due to diverse memory access patterns. The authors present a new concept, called switchable cache, where multiple cache configurations exist on chip, leveraging the abundant transistors available due to what is known as the dark silicon phenomenon. Only one cache configuration is active at any given time based on the application under execution, while all other configurations remain inactive (dark). They describe an architecture to enable seamless integration of multiple cache configurations, and a novel design space exploration methodology to rapidly pre-determine the optimal set of configurations at design-time, for a given group of applications. For design spaces containing trillions of design points, the authors' exploration methodology always found the optimal solution in less than 2 s. The switchable cache improved memory access time by up to 26.2% when compared to a fixed cache.

关键词： cache storage optimisation power aware computing transistors switchable cache dark silicon application specific cache optimisations memory access time energy consumption cache configuration memory access patterns multiple cache configurations transistors exploration methodology

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Pattern Based Cache Coherency Architecture for Embedded Manycores

Pattern Based Cache Coherency Architecture for Embedded Many...

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16th Annual International Conference on Computational Science (ICCS)

作者： Marandola, Jussara Louise, Stephane Cudennec, Loic CEA LIST Saclay France

Modern parallel programming frameworks like OpenMP often rely on shared memory concepts to harness the processing power of parallel systems. But for embedded devices, memory coherence protocols tend to account for a sizable portion of chip's power consumption. This is why any means to lower this impact is important. Our idea for this issue is to use the fact that most of usual workloads display a regular behavior with regards to their memory accesses to prefetch the relevant memory lines in locale caches of execution cores on a manycore system. Our contributions are, on one hand the specifications of a hardware IP for prefetching memory access patterns, and on another hand, a hybrid protocol which extends the classic MESI/baseline architecture to reduce the control and coherence related traffic by at least an order of magnitude. Evaluations are done on several benchmark programs and show the potential of this approach.

关键词： Chip Multi-Processor Cache Coherence Protocol memory access patterns

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Pattern Based Cache Coherency Architecture for Embedded Manycores

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Procedia Computer Science 2016年 80卷 1542-1553页

作者： Jussara Marandola Stephane Louise Loic Cudennec Research work done when employed at CEA LIST CEA LIST Saclay France

关键词： Chip Multi-Processor Cache Coherence Protocol memory access patterns

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