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25th International Conference on Field Programmable Logic and Applications

作者： Umuroglu, Yaman Morrison, Donn Jahre, Magnus Norwegian Univ Sci & Technol Dept Comp & Informat Sci Trondheim Norway

ISBN: (纸本)9781467381239

Large and sparse small-world graphs are ubiquitous across many scientific domains from bioinformatics to computer science. As these graphs grow in scale, traversal algorithms such as breadth-first search (BFS), fundamental to many graph processing applications and metrics, become more costly to compute. The cause is attributed to poor temporal and spatial locality due to the inherently irregular memory access patterns of these algorithms. A large body of research has targeted accelerating and parallelizing BFS on a variety of computing platforms, including hybrid CPU-GPU approaches for exploiting the small-world property. In the same spirit, we show how a single-die FPGA-CPU heterogeneous device can be used to leverage the varying degree of parallelism in small-world graphs. Additionally, we demonstrate how dense rather than sparse treatment of the BFS frontier vector yields simpler memory access patterns for BFS, trading redundant computation for DRAM bandwidth utilization and faster graph exploration. On a range of synthetic small-world graphs, our hybrid approach performs 7.8x better than software-only and 2x better than accelerator-only implementations. We achieve an average traversal speed of 172 MTEPS (millions of traversed edges per second) on the ZedBoard platform, which is more than twice as effective as the best previously published FPGA BFS implementation in terms of traversals per bandwidth.

关键词： breadth-first search (BFS) accelerator architecture matrices over semirings sparse matrix memory access patterns

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Arbitration and Shuffling Algorithm for Processing Multiple Commands in SDRAM Controller

Arbitration and Shuffling Algorithm for Processing Multiple ...

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IEEE International Conference on Consumer Electronics (ICCE)

作者： Lee, Chanho Soongsil Univ Sch Elect Engn Seoul South Korea

ISBN: (纸本)9781479912919

In this paper, we propose an algorithm of arbitration and shuffling of requests for a memory controller which enables high bandwidth, low latency and low power consumption in systems with SoC network protocols that support outstanding address and out-of-order completion transactions. The memory access commands are stored in a queue, analyzed and shuffled in order to minimize activating new rows and to reduce the power consumption in the proposed architecture. It also adjusts the priority of processing commands if the network protocol supports QoS. We compare the performance of the proposed algorithm for the various memory access patterns.

关键词： DRAM chips quality of service system-on-chip QoS SDRAM controller SoC network protocols arbitration algorithm low latency low power consumption memory access commands memory access patterns memory controller multiple commands processing out-of-order completion transactions outstanding address quality of service shuffling algorithm system-on-chips Out of order Protocols Quality of service SDRAM System-on-chip Writing

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The Impact of the SIMD Width on Control-Flow and memory Divergence

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2014年第4期11卷 54-54页

作者： Schaub, Thomas Moll, Simon Karrenberg, Ralf Hack, Sebastian Univ Saarland Dept Comp Sci D-66123 Saarbrucken Germany

Power consumption is a prevalent issue in current and future computing systems. SIMD processors amortize the power consumption of managing the instruction stream by executing the same instruction in parallel on multiple data. Therefore, in the past years, the SIMD width has steadily increased, and it is not unlikely that it will continue to do so. In this article, we experimentally study the influence of the SIMD width to the execution of data-parallel programs. We investigate how an increasing SIMD width (up to 1024) influences control-flow divergence and memory-access divergence, and how well techniques to mitigate them will work on larger SIMD widths. We perform our study on 76 OpenCL applications and show that a group of programs scales well up to SIMD width 1024, whereas another group of programs increasingly suffers from control-flow divergence. For those programs, thread regrouping techniques may become increasingly important for larger SIMD widths. We show what average speedups can be expected when increasing the SIMD width. For example, when switching from scalar execution to SIMD width 64, one can expect a speedup of 60.11, which increases to 62.46 when using thread regrouping. We also analyze the frequency of regular (uniform, consecutive) memory access patterns and observe a monotonic decrease of regular memory accesses from 82.6% at SIMD width 4 to 43.1% at SIMD width 1024.

关键词： Languages Measurement Performance Data parallelism divergent control flow GPGPU memory access patterns OpenCL performance analysis SIMD vectorization

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MAPS: Optimizing Massively Parallel Applications Using Device-Level memory Abstraction

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2014年第4期11卷 44-44页

作者： Rubin, Eri Levy, Ely Barak, Amnon Ben-Nun, Tal Hebrew Univ Jerusalem Dept Comp Sci IL-91904 Jerusalem Israel

GPUs play an increasingly important role in high-performance computing. While developing naive code is straightforward, optimizing massively parallel applications requires deep understanding of the underlying architecture. The developer must struggle with complex index calculations and manual memory transfers. This article classifies memory access patterns used in most parallel algorithms, based on Berkeley's Parallel "Dwarfs." It then proposes the MAPS framework, a device-level memory abstraction that facilitates memory access on GPUs, alleviating complex indexing using on-device containers and iterators. This article presents an implementation of MAPS and shows that its performance is comparable to carefully optimized implementations of real-world applications.

关键词： Parallelism Abstraction Performance GPGPU memory abstraction heterogeneous computing architectures memory access patterns

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A Coarse-grained Stream Architecture for Cryo-electron Microscopy Images 3D Reconstruction 12

A Coarse-grained Stream Architecture for Cryo-electron Micro...

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20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)

作者： Wang, Wendi Duan, Bo Tang, Wen Zhang, Chunming Tan, Guangming Zhang, Peiheng Sun, Ninghui Chinese Acad Sci Inst Comp Technol High Performance Comp Res Ctr Beijing Peoples R China

ISBN: (纸本)9781450311557

The wide acceptance and the data deluge in the bioinformatics and medical imaging processing require more efficient and application-specific systems to be built. Due to the recent advances in FPGAs technologies, there has been a resurgence in research aimed at the design of special-purpose accelerators for standard computer architectures. In this paper, we exploit this trend towards FPGA-based accelerator design and provide a proof-of-concept and comprehensive case study on FPGA-based accelerator design for a single-particle 3D reconstruction application in single-precision floating-point format. The proposed stream architecture is built by first offloading computing-intensive software kernels to dedicated hardware modules, which emphasizes the importance of optimizing computing dominated data access patterns. Then configurable computing streams are constructed by arranging the hardware modules and bypass channels to form a linear deep pipeline. The efficiency of the proposed stream architecture is justified by the reported 2.54 times speedup over a 4-cores CPU. In terms of power efficiency, our FPGA-based accelerator introduces a 7.33 and 3.4 times improvement over a 4-cores CPU and an up-to-date CPU device, respectively.

关键词： Cryo-electron microscopy FFT FPGA stream processing memory access patterns

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High-level timing analysis of concurrent applications on MPSoC platforms using memory-aware trace-driven simulations

High-level timing analysis of concurrent applications on MPS...

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18th IEEE/IFIP International Conference on VLSI and System-on-Chip

作者： Plyaskin, Roman Masrur, Alejandro Geier, Martin Chakraborty, Samarjit Herkersdorf, Andreas Tech Univ Munich Inst Integrated Syst Arcisstr 21 D-80290 Munich Germany Tech Univ Munich Inst Real Time Comp Syst D-80290 Munich Germany

ISBN: (纸本)9781424464708

Due to the growing complexity of multiprocessor systems-on-chip (MPSoCs), there is an increasing demand on efficient design space exploration techniques. In addition to the analysis of diverse hardware architectures, these techniques should assist the designer in the flexible evaluation of various scheduling policies and application mappings while taking effects of the shared on-chip communication infrastructure into account. Most available simulation approaches are either unable to cover all these aspects jointly or have poor simulation performance. In this paper, we present a framework for timing analysis of MPSoC architectures using abstract and yet accurate traces. The traces capture both precise processing latencies and memory access patterns and represent application-and OS-related workload. Performance estimation is performed by an interleaved execution of the traces on a highly configurable multiprocessor platform modeled in our trace-driven SystemC TLM simulator. Using the flexible scheduler model presented in this paper, various mappings and scheduling policies can be rapidly evaluated while considering on-chip interconnect contention and usage of shared resources. Due to the abstraction of the trace-driven simulations, the proposed framework allows for both fast and accurate explorations of MPSoC design alternatives.

关键词： MPSoC architectures MPSoC design OS related workload application mappings computer architecture concurrent application design space exploration technique flexible scheduler model hardware architectures high level timing analysis interleaved execution logic design memory access patterns memory aware trace driven simulation multiprocessing systems multiprocessor platform multiprocessor systems-on-chip on-chip interconnect contention performance estimation processor scheduling scheduling policies shared on-chip communication infrastructure system-on-chip trace driven SystemC TLM simulator trace driven simulations

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Compiler Assisted Cache Prefetch Using Procedure Call Hierarchy

Compiler Assisted Cache Prefetch Using Procedure Call Hierar...

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作者： Doshi, Sheela A Louisiana State University and Agricultural and Mechanical College

学位级别：硕士

Microprocessor performance has been increasing at an exponential rate while memory system performance improved at a linear rate. This widening difference in performances is increasingly rendering advances in computer architecture less useful as more instructions spend more time waiting for data to be fetched from the memory after a cache miss. Data prefetching is a technique that avoids some cache misses by bringing data into the cache before it is actually needed. Different approaches to data prefetching have been developed, however existing prefetch schemes do not eliminate all cache misses and even with smaller cache miss ratio, miss latency remains an important performance limiter. In this thesis, we propose a technique called Compiler Assisted Cache Prefetch Using Procedure Call Hierarchy (CAPPH). It is a hardware-software prefetch technique that uses a compiler to provide information pertaining to data structure layout, data-flow and procedure-call hierarchy of the program to a mechanism that prefetches linked data structures (LDS). It can prefetch data for procedures even before they are called by using this statically generated information. It is also capable of issuing prefetches for recursive functions that access LDS and arbitrary access sequences which are otherwise difficult to prefetch. The scheme is simulated using RSIML, a SPARC v8 simulator. Benchmarks em3d, health and mst from the Olden suite were used. The scheme was compared with an otherwise identical system with no prefetch and one using sequential prefetch. Simulations were performed to measure CAPPH performance and the decrease in the miss ratio of loads accessing LDS. Statistics of individual loads were collected, and accuracy, coverage and timeliness were measured against varying cache size and latency. Results from individual loads accessing linked data structures show considerable decrease in their miss ratios and average access times. CAPPH is found to be more accurate than sequential pr

关键词： linked data structures procedure-call hierarchy sequential & stride patterns memory access patterns prefetch

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MAD kernels: An experimental testbed to study multiprocessor memory system behavior

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1996年第2期7卷 207-217页

作者： Nanda, AK Ni, LM MICHIGAN STATE UNIV DEPT COMP SCIE LANSINGMI 48824

On large-scale multiprocessors, access to common memory is one of the key performance limiting factors. The shared-memory performance depends not only on the characteristics of the memory hierarchy itself, but also upon the characteristics of the memory address streams and the interaction between the two. We present a technique for multiprocessor workload construction and a family of artificial kernels, called MAD-kernels, to systematically investigate the behavior of the memory hierarchy. The measured performance is independent of any particular application or algorithm. The proposed methodology is demonstrated on two commercial shared-memory systems.

关键词： performance evaluation shared-memory multiprocessors memory hierarchy interconnection networks resource contention synchronization overhead memory access patterns

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