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1F-1T array: Current Limiting Transistor Cascoded FeFET memory array for Variation Tolerant Vector-Matrix Multiplication Operation

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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2023年 22卷 424-429页

作者： Sk, Masud Rana Thunder, Sunanda Muller, Franz Laleni, Nellie Raffel, Yannick Lederer, Maximilian Pirro, Luca Chohan, Talha Hsuen, Jing-Hua Wu, Tian-Li Seidel, Konrad Kampfe, Thomas De, Sourav Chakrabarti, Bhaswar IIT Madras Dept Elect Engn Chennai 600036 India CNT Fraunhofer IPMS D-01109 Dresden Germany GlobalFoundries D-01109 Dresden Germany NYCU IPSI Hsinchu 30010 Taiwan NYCU ICST Hsinchu Taiwan

This letter proposes a memory cell, denoted by 1F-1 T, consisting of a ferroelectric field-effect transistor (FeFET) cascaded with another current-limiting transistor (T). The transistor reduces the impact of drain current (I-d) variations by limiting the on-state current in FeFET. The experimental data from our 28 nm high k-metal-gate (HKMG) based FeFET calibrates and simulates the memory arrays. The simulation indicates a significant improvement in bit-line (BL) current (I-BL) variation and the accuracy of vector-matrix multiplication of the 1F-1 T memory array. The system-level in-memory computing simulation with 1F-1T synapses shows an inference accuracy of 97.6% for the MNIST hand-written digits with multi-layer perceptron (MLP) neural networks.

关键词： 1F-1T FeFET HfO2 memory array vector-matrix-multiplication

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On the Feasibility of 1T Ferroelectric FET memory array

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2022年第12期69卷 6722-6730页

作者： Jiang, Zhouhang Zhao, Zijian Deng, Shan Xiao, Yi Xu, Yixin Mulaosmanovic, Halid Duenkel, Stefan Beyer, Sven Meninger, Scott Mohamed, Mohamed Joshi, Rajiv Gong, Xiao Kurinec, Santosh Narayanan, Vijaykrishnan Ni, Kai Rochester Inst Technol Microsyst Engn PhD Program Rochester NY 14623 USA Penn State Univ Dept Elect Engn State Coll PA 16801 USA GlobalFoundries Fab1 LLC & Company KG D-01109 Dresden Germany MIT Lincoln Lab Lexington MA 02421 USA IBM Thomas J Watson Res Ctr Ossining NY 10562 USA Natl Univ Singapore Dept Elect Comp Engn Singapore 119077 Singapore Rochester Inst Technol Dept Elect & Microelect Engn Rochester NY 14623 USA

To fully exploit the ferroelectric field effect transistor (FeFET) as compact embedded nonvolatile memory for various computing and storage applications, it is desirable to use a single FeFET (1T) as a unit cell and arrange the cells into an array. However, many write mechanisms for an 1T FeFET array reported in the literature are yet to be validated experimentally. In this work, we performed a comprehensive experimental characterization on the write operations in an 1T- NOR and 1T- AND array using n-channel bulk FeFETs. We discovered that: 1) the source/drain contact can only supply minority carriers (i.e., electrons) to the channel for polarization screening during the low- ${V}$ TH state programming;2) the body contact can not only supply majority carriers (i.e., holes) for efficient high- ${V}$ TH state write, but also depletion charge for low- ${V}$ TH state programming, though with lower efficiency;and 3) during the low/high- ${V}$ TH programming, only the path that can supply negative/positive screening charges, respectively, need to respond, which necessitates the application of proper write biases on the corresponding terminal. Based on the understanding of these write mechanisms, we show the importance of localized body contact or column-wise body contact for the successful high- ${V}$ TH state programming. We also show that the previously proposed C- AND write scheme fails to program the FeFET to the low- ${V}$ TH state for our devices. Finally, we propose several write schemes for both 1T- AND and 1T- NOR arrays for various scenarios providing insights for choosing the appropriate write scheme, which will facilitate the adoption of 1T FeFET memory arrays for emerging applications.

关键词： Ferroelectric field effect transistor (FeFET) HZO memory array write disturb

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A Scalable ISFET Sensing and memory array With Sensor Auto-Calibration for On-Chip Real-Time DNA Detection

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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 2018年第2期12卷 390-401页

作者： Moser, Nicolas Rodriguez-Manzano, Jesus Lande, Tor Sverre Georgiou, Pantelis Imperial Coll London Ctr Bioinspired Technol Inst Biomed Engn London SW7 2AZ England Imperial Coll London Dept Elect & Elect Engn London SW7 2AZ England

This paper presents a novel CMOS-based system-onchip with a 78 x 56 ion-sensitive field-effect transistor array using in-pixel quantization and compensation of sensor nonidealities. The pixel integrates sensing circuitry and memory cells to encode the ion concentration in time and store a calibration value per pixel. Temperature sensing pixels spread throughout the array allow temperature monitoring during the reaction. We describe the integration of the array as part of a lab-on-chip cartridge that plugs into a motherboard for power management, biasing, data acquisition, and temperature regulation. This forms a robust ion detection platform, which is demonstrated as a pH sensing system. We show that our calibration is able to perform readout with a linear spread of 0.3% and that the system exhibits a high pH sensitivity of 3.2 mu s/pH. The complete system is shown to perform on-chip realtime DNA amplification and detection of lambda phage DNA by loop-mediated isothermal amplification.

关键词： CMOS sensor DNA detection in-pixel quantisation ISFET memory array offset cancellation pH sensor real-time sensor array

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Design of Peripheral Circuits for the Implementation of memory array Using Data-Aware (DA) SRAM Cell in 65 nm CMOS Technology for Low Power Consumption

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JOURNAL OF LOW POWER ELECTRONICS 2016年第1期12卷 9-20页

作者： Singh, Ajay Kumar Saadatzi, Mohammad-Sadegh Venkataseshaiah, C. Multimedia Univ Fac Engn & Technol Melaka 75450 Malaysia

This paper presents the design of the peripheral circuits required to implement a memory array using data-aware (DA) SRAM cell. We used global signal generator circuits to reduce the area overhead. The global generator circuits are connected to their local counterparts through NMOS pass transistors. The column based approach is adopted in which write signal is routed parallel to bitline BL because write signal has to track BL. The adopted design approach in this thesis reduces the number of transistors as well as power consumption in the array. A feedback circuit has been proposed to maintain the data on the unselected cells of the selected row/column in the array due to toggle of the write signal during write operation. The proposed row/column circuitry saves more than 76% power and decodes the address 1.45 x faster than the conventional decoder. Compared to other memory architecture, the proposed architecture saves approximately 74% power at a given power supply and temperature.

关键词： SRAM Cell Power Consumption memory array Peripheral Circuits Read/Write Operation

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Flexible NAND-Like Organic Ferroelectric memory array

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON DEVICE LETTERS 2014年第5期35卷 539-541页

作者： Kam, Benjamin Ke, Tung-Huei Chasin, Adrian Tyagi, Manav Cristoferi, Claudio Tempelaars, Karin van Breemen, Albert J. J. M. Myny, Kris Schols, Sarah Genoe, Jan Gelinck, Gerwin H. Heremans, Paul KU Leuven Dept Elektrotech Dept Elect Engn B-3001 Louvain Belgium IMEC LAE PME B-3001 Heverlee Belgium Amity Univ Noida 201303 India Politecn Torino I-10129 Turin Italy TNO Holst Ctr NL-5656 AE Eindhoven Netherlands

We present a memory array of organic ferroelectric field-effect transistors (OFeFETs) on flexible substrates. The OFeFETs are connected serially, similar to the NAND architecture of flash memory, which offers the highest memory density of transistor memories. We demonstrate a reliable addressing scheme in this architecture, without the need for select or access transistors. As proof of principle, a 1 x 4 NAND-like string is fabricated and characterized. Retention up to one month and endurance up to 2500 cycles are shown. Read and write disturb measurements show that the memory array can potentially be scaled up to 8 kbits.

关键词： Ferroelectric nonvolatile memory organic semiconductors NAND memory array

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A SPICE Model of Resistive Random Access memory for Large-Scale memory array Simulation

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON DEVICE LETTERS 2014年第2期35卷 211-213页

作者： Li, Haitong Huang, Peng Gao, Bin Chen, Bing Liu, Xiaoyan Kang, Jinfeng Peking Univ Inst Microelect Beijing 100871 Peoples R China

A SPICE model of oxide-based resistive random access memory (RRAM) for dc and transient behaviors is developed based on the conductive filament evolution model and is implemented in large-scale array simulation. The simulations of one transistor-one resistor RRAM array up to 16 kb with wire resistance (R-wire) and capacitance (C-wire) indicate that: 1) resistance-capacitance delay during RESET and leakage current during SET have significant impact on write operations;2) with array size enlarging, the power dissipation increases during RESET but decreases during SET;and 3) the increased Rwire and Cwire lead to the degradation of high resistance state and the fluctuation of low resistance state, respectively.

关键词： Circuit simulation memory array power dissipation resistive random access memory (RRAM) SPICE model

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Data Variability Study of Advanced 3D NAND memory using Python 35

Data Variability Study of Advanced 3D NAND Memory using Pyth...

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35th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

作者： Agam, Moshe Mebrahtu, Henok T. Dey, Himadri Intel Foundry Dev Rio Rancho NM 87124 USA

ISBN: (纸本)9798350384567;9798350384550

The methodology for data analysis with large variability based on Python is discussed and demonstrated. As NAND memory transitioned from 2D to 3D, a significant new source of variability emerged due to the stacking of several hundred layers of memory cells on top of each other. This 3D construction demands a novel approach to efficient analysis that allows for a more general overview without sacrificing the details of individual memory cells. The authors explore how to achieve this by identifying sources of variation and systematically parsing and manipulating the data file into smaller files. This methodology enables straightforward visualization of parametric variability in relation to test and process conditions and facilitating the creation of accessible documentation for future reference. The use of Python provides an open-source and user-friendly interface that can be further customized to enhance consistency and reusability.

关键词： 3D NAND NVM memory array Python Variability study Data Analysis

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A 0.5 μm² 2-T Thin-Oxide OTP Antifuse with Reliability Enhanced by Auto Shut-off Program Logic for Low-Power Applications

A 0.5 μm<SUP>2</SUP> 2-T Thin-Oxide OTP Antifuse with Relia...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Li, Haoyu Wang, Dong Zhou, Jiazheng Liu, Junhua Liao, Huailin Peking Univ Beijing Adv Innovat Ctr Integrated Circuits Sch Integrated Circuits Beijing 100871 Peoples R China

ISBN: (纸本)9798350330991;9798350331004

A 2-T Antifuse cell with only thin-oxide transistors is proposed in this work, which is completely compatible with standard CMOS process. Its layout area is only as 0.5 mu m(2) (1x0.5 mu m(2)) in 40nm CMOS process, representing a 67% reduction in size compared with previous work at the same thickness. Considering the bitcell trade-off between area and reliability, the reliability is enhanced by an auto shut-off program logic and its feasibility is proven. Moreover, based on the cell, a 4Kb OTP array simulation shows that the program current is only 7 mu A and read current is 5 mu A. The characteristics of the memory array demonstrate its suitability for low-power applications in systems like RFID.

关键词： Thin-Oxide Antifuse OTP memory array Low Power RFID

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Demonstration of Multiply-Accumulate Operation With 28 nm FeFET Crossbar array

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON DEVICE LETTERS 2022年第12期43卷 2081-2084页

作者： De, Sourav Mueller, Franz Laleni, Nellie Lederer, Maximilian Raffel, Yannick Mojumder, Shaown Vardar, Alptekin Abdulazhanov, Sukhrob Ali, Tarek Duenkel, Stefan Beyer, Sven Seidel, Konrad Kaempfe, Thomas Fraunhofer IPMS Ctr Nanoelect Technol D-01099 Dresden Germany GlobalFoundries D-01109 Dresden Germany

This letter reports a linear multiply-accumulate (MAC) operation conducted on a crossbar memory array based on 28nm high-k metal gate (HKMG) Complementary Metal Oxide Semiconductor (CMOS) and ferroelectric field effect transistor (FeFET). The fabrication is conducted at GlobalFoundries with their standard 28nm technology. The crossbar arrays show a 100% yield in MAC operation on a 300mm wafer. The arrays were divided into 8 x 8 segments. The FeFET crossbar arrays were fabricated with access transistors, current-limiter transistors and a current-mode analog-to-digital converter (ADC) on the same wafer. Finally, the data retention characteristics reveal excellent data retention characteristics up to 5 x 10(4) seconds, which makes this memory array suitable for carrying out MAC operations in inference engine applications.

关键词： Hafnium oxide HfO2 FeFET ferroelectric memory memory array

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Trends and Challenges in Computing-in-memory for Neural Network Model: A Review From Device Design to Application-Side Optimization

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IEEE ACCESS 2024年 12卷 186679-186702页

作者： Yu, Ke Kim, Sunmean Choi, Jun Rim Kyungpook Natl Univ Sch Elect & Elect Engn Daegu 41566 South Korea Kyungpook Natl Univ Sch Elect Engn Coll IT Engn Daegu 41566 South Korea

Neural network models have been widely used in various fields as the main way to solve problems in the current artificial intelligence (AI) field. Efficient execution of neural network models requires devices with massively parallel Multiply-accumulate (MAC) and Matrix-vector Multiplication (MVM) computing capability. However, existing computing devices based on von Neumann architecture suffer from bottlenecks, and the separation of memory and computation module makes data on the move wasting a lot of meaningless computation time and energy. Computing-in-memory (CIM) based on performing MAC computation inside the memory is considered a promising direction to solve this problem. However, large-scale application of CIM still faces challenges due to the non-idealities of current CIM devices and the lack of a common and reliable programmable interface on the application side. In this paper, we will comprehensively analyze the current problems faced by CIMs from various perspectives, such as CIM memory arrays, peripheral circuits, and application-side design, and discuss the possible future development opportunities of CIMs.

关键词： Computational modeling Random access memory Common Information Model (computing) Computer architecture Biological neural networks Artificial intelligence In-memory computing Performance evaluation arrays Voltage Neural network model von Neumann architecture computing-in-memory multiply-accumulate matrix-vector multiplication peripheral circuits memory array

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