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A new relaxed memory consistency model for shared-memory multiprocessors with parallel-multithreaded processing elements

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JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 1998年第4期14卷 785-808页

作者： Wu, CC Chen, C Natl Chiao Tung Univ Dept Comp Sci & Informat Engn Hsinchu 300 Taiwan

The release consistency model is the generally accepted hardware-centric relaxed memory consistency model because of its performance and implementation complexity. By extending the release consistency model, in this paper. we propose a hardware-centric memory consistency model particularly for shared-memory multiprocessor systems with parallel-multithreaded processing elements. The new model uses a new categorization for memory references and utilizes the feature of parallel multithreaded processors (PMPs). We further partition acquire and release references into three sub-categories: one for lock-unlock pairs, one for barrier synchronization, and the last for others. According to the semantic of each synchronization primitive, each sub-category has its own relaxed restrictions. On the other hand, the feature of a PMP is that it is capable of executing more than one thread at the same time, where all parallel threads share only one cache hierarchy. Under the new model, we can use dual write-caches to reduce write traffic and synchronization time. We have used five benchmarks in the SPLASH suite to evaluate the performance gain for the new model. According to the simulation results, the new model is superior to the release consistency model at best by about 11%.

关键词： memory consistency model multithread multiprocessor write cache synchronization PSC model barrier performance evaluation

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PipeGen: Automated Transformation of a Single-Core Pipeline into a Multicore Pipeline for a Given memory consistency model 24

PipeGen: Automated Transformation of a Single-Core Pipeline ...

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International Conference on Parallel Architectures and Compilation Techniques (PACT)

作者： Zhang, An Qi Goens, Andres Oswald, Nicolai Grosser, Tobias Sorin, Daniel Nagarajan, Vijay Univ Utah Salt Lake City UT 84112 USA Univ Amsterdam Amsterdam Netherlands Nvidia Santa Clara CA USA Univ Cambridge Cambridge England Duke Univ Durham NC USA

ISBN: (数字)9798400706318

ISBN: (纸本)9798400706318

Designing a pipeline for a multicore processor is difficult. One major challenge is designing it such that the pipeline correctly enforces the intended memory consistency model (MCM). We have developed the PipeGen design automation tool to allow architects to start with a single core pipeline that only enforces single-threaded correctness and automatically transform it to enforce a given MCM. Our key innovation is a set of compiler-like transformations that codify three different ways of enforcing memory ordering at the pipeline. We have validated that PipeGen correctly enforces the ARMv8 and x86TSO MCMs on three distinct pipeline implementations, using litmus tests with the Murphi model checker.

关键词： memory consistency model Computer Architecture Microarchitecture Programming Language Compiler

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Grouping memory consistency model for parallel-multithreaded shared-memory multiprocessor systems

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INTERNATIONAL JOURNAL OF HIGH SPEED COMPUTING 1999年第1期10卷 53-81页

作者： Wu, CC Chen, C Natl Chiao Tung Univ Dept Comp Sci & Informat Engn Hsinchu Taiwan

In this paper, we propose a hardware-centric memory consistency model particularly for shared-memory multiprocessors with parallel-multithreaded processing elements. According to the behavior of critical sections and the feature of parallel-multithreaded processors, we extend the release consistency model to a more relaxed memory model. A release reference at the end of a critical section can be executed locally regardless of whether all of its previous ordinary references have performed. The requirement is that another thread on the same processor is waiting for the lock to be freed. Two new instructions and two additional macros are needed to properly label a program for our proposed model. Moreover, we use a table per processing element to determine if there are any threads waiting for a specific lock. We have used five benchmark programs in the SPLASH suite to evaluate the performance gain for the new model. According to the simulation results, our proposed model is superior to the release consistency model up to 25%.

关键词： memory consistency model multithread multiprocessor synchronization grouping consistency model performance evaluation

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A general model checking framework for various memory consistency models

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INTERNATIONAL JOURNAL ON SOFTWARE TOOLS FOR TECHNOLOGY TRANSFER 2017年第5期19卷 623-647页

作者： Abe, Tatsuya Maeda, Toshiyuki RIKEN Adv Inst Computat Sci Chuo Ku 7-1-26 Minatojima Minami Machi Kobe Hyogo 6500047 Japan

Relaxed memory consistency models are common and essential when multiple processes share a single global address space, such as when using multicore CPUs, distributed shared-memory programming languages, and so forth. Programming within these models is difficult and error prone, because of non-intuitive behaviors that could not occur in a strict consistency model. In addition, because the memory consistency models vary from language to language, and CPU to CPU, a program that may work correctly on one system may not work on another. To address the problem, this paper describes a model checking framework in which users are able to check their programs under various memory consistency models. More specifically, our framework provides a base model that exhibits very relaxed behaviors, and users are able to define various consistency models by adding constraints to the base model. This paper also describes McSPIN, a prototype implementation of a model checker based on the proposed framework. McSPIN can take a memory consistency model as an input, as well as a program and a property to be checked. We have specified the necessary constraints for three practical existing memory consistency models (Unified Parallel C, Coarray Fortran, and Itanium). McSPIN verified some example programs correctly, and confirmed the expected differences among the three models.

关键词： memory consistency model model checking Unified Parallel C Coarray Fortran Itanium

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A General model Checking Framework for Various memory consistency models 28

A General Model Checking Framework for Various Memory Consis...

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28th IEEE International Parallel & Distributed Processing Symposium Workshops (IPDPSW)

作者： Abe, Tatsuya Maeda, Toshiyuki RIKEN Adv Inst Computat Sci Kobe Hyogo Japan

ISBN: (纸本)9781479941162

Relaxed memory consistency models are common and essential when multiple processes share a single global address space, such as when using multicore CPUs, partitioned global address space languages, and so forth. Programming within these models is difficult and error prone, because of non-intuitive behaviors that could not occur in a sequential memory consistency model. In addition, because the memory consistency models vary from language to language, and CPU to CPU, a program which may work correctly on one system may not work on another. To address the problem, this paper describes a model checking framework in which users are able to check their programs under various memory consistency models. More specifically, our framework provides a base model that exhibits very relaxed behaviors, and users are able to define various consistency models by adding constraints to the base model. This paper also describes a prototype implementation of a model checker based on the proposed framework. We have specified the necessary constraints for three practical existing memory consistency models (UPC, Coarray Fortran, and Itanium). Our model checker verified some example programs correctly, and confirmed the expected differences among the three models.

关键词： memory consistency model model checking Unified Parallel C Coarray Fortran Itanium

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VERIFYING CORRECT MICROARCHITECTURAL ENFORCEMENT OF memory consistency modelS

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IEEE MICRO 2015年第3期35卷 72-82页

作者： Lustig, Daniel Pellauer, Michael Martonosi, Margaret Princeton Univ Dept Elect Engn Princeton NJ 08544 USA Nvidia Santa Clara CA 95050 USA Princeton Univ Comp Sci Princeton NJ 08544 USA

memory consistency modelS DEFINE THE RULES AND GUARANTEES ABOUT THE ORDERING AND VISIBILITY OF memory REFERENCES ON MULTITHREADED CPUS AND SYSTEMS ON CHIP. PIPECHECK OFFERS A METHODOLOGY AND AUTOMATED TOOL FOR VERIFYING THAT A PARTICULAR MICROARCHITECTURE CORRECTLY IMPLEMENTS THE consistency model REQUIRED BY ITS ARCHITECTURAL SPECIFICATION.

关键词： Analytical models Buffer storage computer architecture formal verification Load modeling memory architecture memory consistency model Microarchitecture PipeCheck Pipelines processor microarchitecture Program processors Radio frequency

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MTraceCheck: Validating Non-Deterministic Behavior of memory consistency models in Post-Silicon Validation 17

MTraceCheck: Validating Non-Deterministic Behavior of Memory...

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44th Annual International Symposium on Computer Architecture (ISCA)

作者： Lee, Doowon Bertacco, Valeria Univ Michigan Ann Arbor MI 48109 USA

ISBN: (纸本)9781450348928

This work presents a minimally-intrusive, high-performance, post-silicon validation framework for validating memory consistency in multi-core systems. Our framework generates constrained-random tests that are instrumented with observability-enhancing code for memory consistency verification. For each test, we generate a set of compact signatures reflecting the memory-ordering patterns observed over many executions of the test, with each of the signatures corresponding to a unique memory-ordering pattern. We then leverage an efficient and novel analysis to quickly determine if the observed execution patterns represented by each unique signature abide by the memory consistency model. Our analysis derives its efficiency by exploiting the structural similarities among the patterns observed. We evaluated our framework, MTraceCheck, on two platforms: an x86-based desktop and an ARM-based SoC platform, both running multi-threaded test programs in a bare-metal environment. We show that MTraceCheck reduces the perturbation introduced by the memory-ordering monitoring activity by 93% on average, compared to a baseline register flushing approach that saves the register's state after each load operation. We also reduce the computation requirements of our consistency checking analysis by 81% on average, compared to a conventional topological sorting solution. We finally demonstrate the effectiveness of MTraceCheck on buggy designs, by evaluating multiple case studies where it successfully exposes subtle bugs in a full-system simulation environment.

关键词： memory consistency model post-silicon validation

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Compiler optimisations and relaxed memory consistency models

Compiler optimisations and relaxed memory consistency models

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作者： Robin Morisset Ecole Normale Superieure

学位级别：博士

Modern multiprocessors architectures and programming languages exhibit weakly consistent memories. Their behaviour is formalised by the memory model of the architecture or programming language; it precisely defines which write operation can be returned by each shared memory read. This is not always the latest store to the same variable, because of optimisations in the processors such as speculative execution of instructions, the complex effects of caches, and optimisations in the compilers. In this thesis we focus on the C11 memory model that is defined by the 2011 edition of the C standard. Our contributions are threefold. First, we focused on the theory surrounding the C11 model, formally studying which compiler optimisations it enables. We show that many common compiler optimisa- tions are allowed, but, surprisingly, some important ones are forbidden. Secondly, building on our results, we developed a random testing methodology for detecting when mainstream compilers such as GCC or Clang perform an incorrect optimisation with respect to the memory model. We found several bugs in GCC, all promptly fixed. We also implemented a novel optimisation pass in LLVM, that looks for special instructions that restrict processor optimisations - called fence instructions - and eliminates the redundant ones. Finally, we developed a user-level scheduler for lightweight threads communicating through first-in first- out single-producer single-consumer queues. This programming model is known as Kahn process networks, and we show how to efficiently implement it, using C11 synchronisation primitives. This shows that despite its flaws, C11 can be usable in practice.

关键词： memory model memory consistency model C11 Compiler optimisations Fence

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Chip Multithreaded consistency model

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Journal of Computer Science & Technology 2008年第2期23卷 298-304,F0003页

作者：李祖松郇丹丹胡伟武唐志敏 Institute of Computing Technology Chinese Academy of SciencesBeijing 100080China

Multithreaded technique is the developing trend of high performance processor. memory consistency model is essential to the correctness, performance and complexity of multithreaded processor. The chip multithreaded consistency model adapting to multithreaded processor is proposed in this paper. The restriction imposed on memory event ordering by chip multithreaded consistency is presented and formalized. With the idea of critical cycle built by Wei-Wu Hu, we prove that the proposed chip multithreaded consistency model satisfies the criterion of correct execution of sequential consistency model. Chip multithreaded consistency model provides a way of achieving high performance compared with sequential consistency model and easures the compatibility of software that the execution result in multithreaded processor is the same as the execution result in uniprocessor. The implementation strategy of chip multithreaded consistency model in Godson-2 SMT processor is also proposed. Godson-2 SMT processor supports chip multithreaded consistency model correctly by exception scheme based on the sequential memory access queue of each thread.

关键词： computer architecture Godson-2 multithreading memory consistency model event ordering

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TC-Release plus plus : An Efficient Timestamp-Based Coherence Protocol for Many-Core Architectures

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2017年第11期28卷 3313-3327页

作者： Yao, Yuan Chen, Wenzhi Mitra, Tulika Xiang, Yang Zhejiang Univ Sch Comp Sci & Technol Hangzhou 310027 Zhejiang Peoples R China Natl Univ Singapore Sch Comp Singapore 119077 Singapore Swinburne Univ Technol Swinburne Res Hawthorn Vic 3122 Australia

As we enter the era of many-core, providing the shared memory abstraction through cache coherence has become progressively difficult. The standard directory-based coherence does not scale well with increasing core count. Timestamp-based hardware coherence protocols introduced recently offer an attractive alternative solution. This paper proposes a timestamp-based coherence protocol, called TC-Release++, that efficiently supports cache coherence in large-scale systems. Our approach is inspired by TC-Weak, a recently proposed timestamp-based coherence protocol targeting GPU architectures. We first design TC-Release in an attempt to straightforwardly port TC-Weak to general-purpose many-cores. But re-purposing TC-Weak for general-purpose many-core architectures is challenging due to significant differences both in architecture and the programming model. Indeed the performance of TC-Release turns out to be worse than conventional directory protocols. We overcome the limitations and overheads of TC-Release by exploiting simple hardware support to eliminate frequent memory stalls, and an optimized lifetime prediction mechanism to improve cache performance. The resulting optimized coherence protocol TC-Release++ is highly scalable (storage scales logarithmically with core count) and shows better performance (3.0 percent) and comparable network traffic (within 1.3 percent) relative to the baseline MESI directory protocol. We use Murphi to formally verify that TC-Release++ is error-free and imposes small verification cost.

关键词： Cache coherence many-core architecture timestamp-based system memory consistency model

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