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检索条件"主题词=Memory Model"

共 138 条记录，以下是91-100 订阅

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HICAMP: Architectural Support for Efficient Concurrency-safe Shared Structured Data Access

HICAMP: Architectural Support for Efficient Concurrency-safe...

引用

17th International Conference on Architectural Support for Programming Languages and Operating Systems

作者： Cheriton, David Firoozshahian, Amin Solomatnikov, Alex Stevenson, John P. Azizi, Omid Hicamp Syst Inc Menlo Pk CA 94025 USA Stanford Univ Stanford CA 94305 USA

ISBN: (纸本)9781450307598

Programming language and operating system support for efficient concurrency-safe access to shared data is a key concern for the effective use of multi-core processors. Most research has focused on the software model of multiple threads accessing this data within a single shared address space. However, many real applications are actually structured as multiple separate processes for fault isolation and simplified synchronization. In this paper, we describe the HICAMP architecture and its innovative memory system, which supports efficient concurrency-safe access to structured shared data without incurring the overhead of inter-process communication. The HICAMP architecture also provides support for programming language and OS structures such as threads, iterators, read-only access and atomic update. In addition to demonstrating that HICAMP is beneficial for multi-process structured applications, our evaluation shows that the same mechanisms provide substantial benefits for other areas, including sparse matrix computations and virtualization.

关键词： Design Performance Reliability Parallel Programming Parallel Architecture memory model Snapshot Semantics memory Sharing Fault Isolation memory Deduplication Iterator Register

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Giving an Office Assistant Agent a memory Mechanism

Giving an Office Assistant Agent a Memory Mechanism

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7th IEEE International Conference on Cognitive Informatics (ICCI 2008)

作者： Chen, Ke-Jia Barthes, Jean-Paul Univ Technol Compiegne CNRS UMR Heudiasyc 6599 F-60206 Compiegne France

ISBN: (纸本)9781424425389

The extension of ubiquitous computing leads to building networks linking people and services. One problem is to interface humans with such networks. Due to the distributed aspect of the new environment, we advocate to use "intelligent" Personal Assistant agents. Thus, our view of a Personal Assistant (PA) agent is that of an intelligent agent capable of helping users to handle tasks in their workplace. The paper explains how to give a PA agent a memory mechanism, which results in an improved PA agent: MemoPA. Inspired by a case memory model in the domain of Case-Based Reasoning (CBR), we give a PA agent a structured memory. Then, a cognitive memory processor is built to monitor and to update the memory. A first prototype of MemoPA has been developed and implemented on a multi-agent platform named OMAS. The paper indicates how the memory, mechanism makes the PA agent more efficient in handling the tasks requested by the user and in the processing of the user's requests. Finally, several possible improvements for the memory mechanism are discussed

关键词： Multi-Agent Systems Personal Assistant Agents memory model Case-Based Reasoning

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Generalized ERSS tree model: Revisiting working sets

Generalized ERSS tree model: Revisiting working sets

引用

Conference on Performance Evaluation 2010

作者： Koller, Ricardo Verma, Akshat Rangaswami, Raju Florida Int Univ Sch Comp & Informat Sci Miami FL 33199 USA

Accurately characterizing the resource usage of an application at various levels in the memory hierarchy has been a long-standing research problem Existing characterization studies are either motivated by specific allocation problems (e g memory page allocation) or they characterize a specific memory resource (e g. 12 cache) The studies thus far have also implicitly assumed that there is no contention for the resource under consideration The inevitable future of virtualization driven consolidation necessitates the sharing of physical resources at all levels of the memory hierarchy by multiple virtual machines (VMs) Given the lack of resource isolation mechanisms at several levels of the memory hierarchy within current commodity systems provisioning resources for a virtualized application not only requires a precise characterization of its resource usage but must also account for the Impact of resource contention due to other co-located applications during its lifetime In this paper, we present a unifying Generalized ERSS Tree model that characterizes the resource usage at all levels of the memory hierarchy during the entire lifetime of an application Our model characterizes capacity requirements the rate of use and the impact of resource contention, at each level of memory We present a methodology to build the model and demonstrate how it can be used for the accurate provisioning of the memory hierarchy in a consolidated environment Empirical results suggest that the Generalized ERSS Tree model is effective at characterizing applications with a wide variety of resource usage behaviors (C) 2010 Elsevier B V All rights reserved

关键词： memory model Cache contention Performance isolation Server consolidation

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Synchronization Using Remote-Scope Promotion 15

Synchronization Using Remote-Scope Promotion

引用

20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

作者： Orr, Marc S. Che, Shuai Yilmazer, Ayse Beckmann, Bradford M. Hill, Mark D. Wood, David A. Univ Wisconsin Madison Comp Sci Madison WI 53706 USA AMD Res Hyderabad Andhra Pradesh India

ISBN: (纸本)9781450328357

Heterogeneous system architecture (HSA) and OpenCL (TM) define scoped synchronization to facilitate low overhead communication across a subset of threads. Scoped synchronization works well for static sharing patterns, where consumer threads are known a priori. It works poorly for dynamic sharing patterns (e.g., work stealing) where programmers cannot use a faster small scope due to the rare possibility that the work is stolen by a thread in a distant slower scope. This puts programmers in a conundrum: optimize the common case by synchronizing at a faster small scope or use work stealing at a slower large scope. In this paper, we propose to extend scoped synchronization with remote-scope promotion. This allows the most frequent sharers to synchronize through a small scope. Infrequent sharers synchronize by promoting that remote small scope to a larger shared scope. Synchronization using remote-scope promotion provides performance robustness for dynamic workloads, where the benefits provided by scoped synchronization and work stealing are hard to anticipate. Compared to a naive baseline, static scoped synchronization alone achieves a 1.07x speedup on average and dynamic work stealing alone achieves a 1.18x speedup on average. In contrast, synchronization using remote-scope promotion achieves a robust 1.25x speedup on average, across a diverse set of graph benchmarks and inputs.

关键词： graphics processing unit (GPU) memory model scope promotion scoped synchronization work stealing

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Fully Detection of Illegal memory Access Defects 10

Fully Detection of Illegal Memory Access Defects

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10th International Conference on Complex, Intelligent, and Software Intensive Systems (CISIS)

作者： Dong, Yukun China Univ Petr Coll Comp & Commun Engn Qingdao Shandong Peoples R China

ISBN: (纸本)9781509009879

There are many illegal memory access (IMA) defects in C programs, for example, null pointer dereference, buffer overflow and array out of bounds. When C programs are running, these defects may cause software failure, and may lead to serious consequences. In order to fully detect these IMA defects, we apply abstract regions to simulate memory blocks that allocated to memory objects at the runtime, and use the region-based model to describe memory states of each program point based on the result of dataflow analysis. Based on the region-based model, the determining criterion of IMA defects is introduced for detecting these defects. The method has been implemented in the defect detection tool DTSC, and 5 open source projects are tested, the test results show the validity of our method.

关键词： memory defects memory model defect detection dataflow analysis

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Analysis of MPI Shared-memory Communication Performance from a Cache Coherence Perspective 28

Analysis of MPI Shared-Memory Communication Performance from...

引用

28th IEEE International Parallel & Distributed Processing Symposium Workshops (IPDPSW)

作者： Putigny, Bertrand Ruelle, Benoit Goglin, Brice Inria Bordeaux Sud Ouest Bordeaux France Bordeaux Polytech Inst Bordeaux France

ISBN: (纸本)9781479941162

Shared memory MPI communication is an important part of the overall performance of parallel applications. However understanding the behavior of these data transfers is difficult because of the combined complexity of modern memory architectures with multiple levels of caches and complex cache coherence protocols, of MPI implementations, and of application needs. We analyze shared memory MPI communication from a cache coherence perspective through a new memory model. It captures the memory architecture characteristics with micro-benchmarks that exhibit the limitations of the memory accesses involved in the data transfer. We model the performance of intra-node communication without requiring complex analytical models. The advantage of the approach consists in not requiring deep knowledge of rarely documented hardware features such as caching policies or prefetchers that make modeling modern memory subsystems hardly feasible. Our qualitative analysis based on this result leads to a better understanding of shared memory communication performance for scientific computing. We then discuss some possible optimizations such as buffer reuse order, cache flushing, and non-temporal instructions that could be used by MPI implementers.

关键词： Cache coherence memory model MPI Shared-memory communication

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A Formal CHERI-C Semantics for Verification 29th

A Formal CHERI-C Semantics for Verification

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29th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS)

作者： Park, Seung Hoon Pai, Rekha Melham, Tom Univ Oxford Dept Comp Sci Oxford England

ISBN: (纸本)9783031308222;9783031308239

CHERI-C extends the C programming language by adding hardware capabilities, ensuring a certain degree of memory safety while remaining efficient. Capabilities can also be employed for higher-level security measures, such as software compartmentalization, that have to be used correctly to achieve the desired security guarantees. As the extension changes the semantics of C, new theories and tooling are required to reason about CHERI-C code and verify correctness. In this work, we present a formal memory model that provides a memory semantics for CHERI-C programs. We present a generalised theory with rich properties suitable for verification and potentially other types of analyses. Our theory is backed by an Isabelle/HOL formalisation that also generates an OCaml executable instance of the memory model. The verified and extracted code is then used to instantiate the parametric Gillian program analysis framework, with which we can perform concrete execution of CHERI-C programs. The tool can run a CHERI-C test suite, demonstrating the correctness of our tool, and catch a good class of safety violations that the CHERI hardware might miss.

关键词： CHERI-C Hardware Capabilities memory model Semantics Theorem Proving Verification

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Verification of the Java causality requirements

Verification of the Java causality requirements

引用

1st International Haifa Verification Conference

作者： Polyakov, S Schuster, A Technion Israel Inst Technol Dept Comp Sci Technion Haifa Israel

ISBN: (纸本)3540326049

The Java memory model (JMM) formalizes the behavior of shared memory accesses in a multithreaded Java program. Dependencies between memory accesses are acyclic, as defined by the JMM causality requirements. We study the problem of post-mortem verification of these requirements and prove that the task is NP-complete. We then argue that in some cases the task may be simplified either by considering a slightly stronger memory model or by tracing the actual execution order of Read actions in each thread. Our verification algorithm has two versions: a polynomial version, to be used when one of the aforementioned simplifications is possible, and a non-polynomial version - for short test sequences only - to be used in all other cases. Finally, we argue that the JMM causality requirements could benefit from some fine-tuning. Our examination of causality test case 6 (presented in the public discussion of the JMM) clearly shows that some useful compiler optimizations - which one would expect to be permissible - axe in fact prohibited by the formal model.

关键词： concurrency complexity Java memory model multi-threading verification shared memory

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Lazy Release Consistency for GPUs 49

Lazy Release Consistency for GPUs

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49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Alsop, Johnathan Orr, Marc S. Beckmann, Bradford M. Wood, David A. Univ Illinois Champaign IL 61801 USA Univ Wisconsin Madison WI 53706 USA AMD Res Sunnyvale CA USA

ISBN: (纸本)9781509035083

The heterogeneous-race-free (HRF) memory model has been embraced by the Heterogeneous System Architecture (HSA) Foundation and OpenCL (TM) because it clearly and precisely defines the behavior of current GPUs. However, compared to the simpler SC for DRF memory model, HRF has two shortcomings. The first is that HRF requires programmers to label atomic memory operations with the correct scope of synchronization. This explicit labeling can save significant coherence overhead when synchronization is local, but it is tedious and error-prone. The second shortcoming is that HRF restricts important dynamic data sharing patterns like work stealing. Prior work on remote-scope promotion (RSP) attempted to resolve the second shortcoming. However, RSP further complicates the memory model and no scalable implementation of RSP has been proposed. For example, we found that the previously proposed RSP implementation actually results in slowdowns of up to 30% on large GPUs, compared to a naive baseline system that forgoes work stealing and scopes. Meanwhile, DeNovo has been shown to offer efficient synchronization with an SC for DRF memory model, performing on average 21% better than our baseline system, but it introduces additional overheads to maintain ownership of all modified data. To resolve these deficiencies, we propose to adapt lazy release consistency-previously only proposed for homogeneous CPU systems-to a heterogeneous system. Our approach, called hLRC, uses a DeNovo-like mechanism to track ownership of synchronization variables, lazily performing coherence actions only when a synchronization variable changes locations. hLRC allows GPU programmers to use the simpler SC for DRF memory model without tracking ownership for all modified data. Our evaluation shows that lazy release consistency provides robust performance improvement across a set of work-stealing graph analysis applications-29% on average versus the baseline system.

关键词： graphics processing unit (GPU) memory model lazy release consistency scope promotion scoped synchronization work stealing

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Fail memory Configuration Set for RA Estimation

Fail Memory Configuration Set for RA Estimation

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IEEE International Test Conference (ITC)

作者： Lee, Hayoung Cho, Keewon Kang, Sungho Kang, Wooheon Lee, Seungtaek Jeong, Woosik Yonsei Univ Dept Elect & Elect Engn Seoul South Korea SK Hynix Inc Icheon South Korea

ISBN: (纸本)9781728191133

Since the redundancy analysis (RA) has been introduced for memory yield, many RA researches have been conducted. However, objective comparisons of them are difficult by the absence of real memory models with realistic fault distributions. This paper presents a fail memory configuration set for RA estimation, called as ITC'2020 RA Benchmarks. It enables objective estimations of RAs with respect to effectiveness and efficiency. The fail memory configuration set includes memory models which have various redundancy structures and a fault generation algorithm with fault distribution which can be criteria for objective comparisons of RA. Simulations for estimations and comparisons of RA researches including BIRA are progressed utilizing the fail memory configuration set.

关键词： redundancy analysis (RA) built-in RA (BIRA) benchmark memory model fault distribution redundancy structure repair rate analysis time

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