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Comprehensive Review on the Exploitation of Advanced memory optimization Strategies to Improve Performance for Convolutional and Spiking Neural Networks in Medical Imaging Using Hardware Accelerators

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IEEE ACCESS 2025年 13卷 62449-62461页

作者： Prasad, N. Srikanth Sundar, S. Vellore Inst Technol Sch Elect Engn SENSE Vellore 632014 Tamil Nadu India

Advanced memory optimization techniques are reviewed to enhance the performance of Convolutional Neural Networks (CNNs) and Spiking Neural Networks (SNNs) on hardware accelerators, addressing the real-world challenges in medical imaging. This review evaluates various platforms: In-memory Computing (IMC), Field-Programmable Gate Array (FPGA), Python Productivity for Zynq (PYNQ-Z2), Graphics Processing Unit (GPU), and Application-Specific Integrated Circuit (ASIC) concerning overcoming memory bottlenecks, minimizing latency, and reducing energy consumption in Magnetic Resonance Imaging (MRI) reconstruction, Computed Tomography (CT) scan analysis, and real-time diagnostics. It will analyze techniques like memory compression, tiling, hierarchical memory management, and neural network pruning to improve computation efficiency. In addition, in-memory computing will be a key focus to mitigate the inefficiency of data movement, adaptability of Field-Programmable Gate Array (FPGA) for custom workloads, parallel processing by Graphics Processing Unit (GPU), and domain-specific optimizations of Application-Specific Integrated Circuit (ASIC). This review addresses the challenges of high-resolution image processing and energy constraints to provide a comprehensive guide to scalable, efficient hardware accelerators for neural networks in medical imaging.

关键词： optimization Field programmable gate arrays Neural networks Hardware acceleration Medical diagnostic imaging In-memory computing Real-time systems Graphics processing units Energy efficiency Reviews memory optimization neural networks FPGA in-memory computing medical imaging hardware accelerators

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memory optimization of MAP turbo decoder algorithms

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2001年第2期9卷 305-312页

作者： Schurgers, C Catthoor, F Engels, M IMEC B-3001 Heverlee Belgium Katholieke Univ Leuven Dept Elect Engn Louvain Belgium

Turbo codes are the most recent breakthrough in coding theory. However, the decoder's implementation cost limits their incorporation in commercial systems, Although the decoding algorithm is highly data dominated, no true memory optimization study has been performed yet. We have extensively and systematically investigated different memory optimizations for the maximum a posteriori (MAP) class of decoding algorithms. It turns out that it is not possible to present one decoder structure as being optimal. In bet, there are several tradeoffs, which depend on the specific turbo code, the implementation target (hardware or software), and the selected cost function, We therefore end up with a parametric family of new optimized algorithms out of which the designer can choose. The impact of our optimizations is illustrated by a representative example, which shows a significant decrease in both decoding energy (factor 2.5) and delay (factor 1.7).

关键词： maximum a posteriori (MAP) algorithm memory optimization turbo codes

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memory optimization of CNN Heterogeneous Multi-Core Architecture 4

Memory Optimization of CNN Heterogeneous Multi-Core Architec...

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4th International Conference on Integrated Circuits and Microsystems (ICICM)

作者： Gao, Muxuan Liu, Dake Miao, Zhidong Liu, Shaohan Beijing Inst Technol Sch Informat & Elect Beijing Peoples R China

ISBN: (纸本)9781728151328

Convolutional neural networks(CNNs) computing complexity raises challenges to the power and cost of CNN accelerators. The power consumption and delay of the data access between on-chip and off-chip memories have been a bottleneck of the on-chip system for CNN acceleration. We propose a static scheduling framework based on our heterogeneous programmable multi-core ASIP (Application Specific Instruction-set Processor) for inference of deep learning. This scheduling framework minimizes power consumption and promotes performance under the hardware resource limitation, including datapath computing capability, access bandwidth limitation, and on-chip memory size. We also discussed how to achieve theoretical maximum performance for a set of fixed hardware constraints. Comparing to the scheduling on DNA(deep neural architecture) under the same AlexNet platform, our scheduling achieves 11.8% more average resource utilization. By reusing and broadcasting local data, the average DRAM access of our design is reduced down to 41% of the access of DNA. The estimated power consumption of this design is 35% lower than the power of DNA, mostly because of the power reduction from DDR data accesses. Meanwhile, through the ping-pang memory and the careful design of data partition, the time of data access between DRAM and SRAM is reduced 77% by access hidden.

关键词： component convolutional neural network(CNN) memory optimization static schedule

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memory optimization of a Distributed Middleware for Smart Grid Applications 2

Memory Optimization of a Distributed Middleware for Smart Gr...

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2nd International Conference on Internet of Things, Big Data and Security (IoTBDS)

作者： Cejka, Stephan Frischenschlager, Albin Faschang, Mario Stefan, Mark Siemens AG Corp Technol Res Digitalizat & Automat Siemensstr 90 A-1210 Vienna Austria AIT Austrian Inst Technol GmbH Energy Dept Donau City Str 1 A-1220 Vienna Austria

ISBN: (纸本)9789897582455

In order to exploit the full potential of IoT-enabled power distribution grids, Smart Grid applications are developed. Their operation on resource-constraint automation devices requires for memory optimized operation. In this paper we present field-approved operation and management solutions for Smart Grid applications, based on a distributed middleware. We introduce a new entity to allow for dynamically loading Smart Grid applications within one JVM. Presented experiments demonstrate the reduction of the memory footprint on the physical device.

关键词： IoT Application Management Distributed Smart Grid Applications Java Virtual Machine memory optimization

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memory optimization Paradigm for High Performance Energy Efficient GPU 2nd

Memory Optimization Paradigm for High Performance Energy Eff...

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2nd International Conference on Information and Communication Technology for Intelligent Systems (ICTIS)

作者： Voora, Prashanth Anand, Vipin Patel, Nilaykumar Intel Technol India Private Ltd Bangalore 560103 Karnataka India

ISBN: (纸本)9783319636733;9783319636726

The following paper propose a new memory management technique of handling the GState's in DDK and the same can be extended for sending command buffer which hold the job request to various USM/UVC blocks in GPU. We shall discuss the most generic design followed across various device driver and explains the drawback of using the existing design and introduce the new memory management technique along with some futuristic improvements. This design philosophy is more suited in GPU architecture's which have deferred multi-pass rendering for 3D graphics pipeline.

关键词： GPU Low-power memory optimization Deferred rendering 3G graphics pipeline G-State Command buffer

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A memory optimization method combined with adaptive time-step method for cardiac cell simulation based on multi-GPU

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MEDICAL & BIOLOGICAL ENGINEERING & COMPUTING 2020年第11期58卷 2821-2833页

作者： Luo, Ching-Hsing Ye, Haiyi Chen, Xingji Sun Yat Sen Univ Sch Data & Comp Sci Guangzhou Guangdong Peoples R China Sun Yat Sen Univ Affiliated Hosp 3 Guangzhou Guangdong Peoples R China Hezhou Univ Modern Ind Coll Sch Artificial Intelligence Hezhou Guangxi Peoples R China

Cardiac electrophysiological simulation is a very complex computational process, which can be run on graphics processing unit (GPU) to save computational cost greatly. The use of adaptive time-step can further effectively speed up the simulation of heart cells. However, if the adaptive time-step method applies to GPU, it suffers synchronization problem on GPU, weakening the acceleration of adaptive time-step method. The previous work ran on a single GPU with the adaptive time-step to get only 1.5 times (x 1.5) faster than the fixed time-step. This study proposes a memory allocation method, which can effectively implement the adaptive time-step method on GPU. The proposed method mainly focuses on the stimulus point and potential memory arrangement in order to achieve optimal memory storage efficiency. All calculation is implemented on GPU. Large matrices such as potential are arranged in column order, and the cells on the left are stimulated. The Luo-Rudy passive (LR1) and dynamic (LRd) ventricular action potential models are used with adaptive time-step methods, such as the traditional hybrid method (THM) and Chen-Chen-Luo's (CCL) "quadratic adaptive algorithm" method. As LR1 is solved by the THM or CCL on a single GPU, the acceleration is x 34 and x 75 respectively compared with the fixed time-step. With 2 or 4 GPUs, the acceleration of the THM and CCL is x 34 or x 35 and x 73 or x 75, but it would decrease to x 5 or x 3 and x 20 or x 15 without optimization. In an LRd model, the acceleration reaches x 27 or x 85 as solved by the THM or CCL compared with the fixed time-step on multi-GPU with linear speed up increase versus the number of GPU. However, with the increase of GPUs number, the acceleration of the THM and CCL is continuously weakened before optimization. The mixed root mean square error (MRMSE) lower than 5% is applied to ensure the accuracy of simulation. The result shows that the proposed memory arrangement method can save computational cost a lot to sp

关键词： Computer simulation Ventricular cell High performance computing Adaptive time-step method memory optimization

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Split: A Hash-Based memory optimization Method for Zero-Knowledge Succinct Non-Interactive Argument of Knowledge (zk-SNARK)

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IEEE TRANSACTIONS ON COMPUTERS 2023年第7期72卷 1857-1870页

作者： Qi, Huayi Cheng, Ye Xu, Minghui Yu, Dongxiao Wang, Haipeng Lyu, Weifeng Shandong Univ Sch Comp Sci & Technol Qingdao 266237 Peoples R China Naval Aviat Univ Inst Informat Fus Yantai 264001 Peoples R China Beihang Univ Sch Comp Sci & Technol Beijing 100191 Peoples R China

Zero-Knowledge Succinct Non-Interactive Argument of Knowledge (zk-SNARK) is a practical zero-knowledge proof system for Rank-1 Constraint Satisfaction (R1CS), enabling privacy preservation and addressing the previous scalability concerns on zero-knowledge proofs. Existing constructions of zk-SNARKs require huge memory overhead to generate proofs in that the size of the zk-SNARK circuit can be large even for a very simple use case, which limits the applications for regular resource-constrained users. To reduce the memory utilization of zk-SNARKs, this paper presents a hash-based method "Split". Concretely, Split intends to partition the zk-SNARK circuits so that components can be processed sequentially while ensuring strong security properties leveraging hash circuits. As a zk-SNARK circuit is partitioned, obsolete variables are no longer preserved in the memory. We further propose an enhanced Split as $n$n-Split, which leads to better optimization by properly choosing multiple splits. Our experimental results validate the effectiveness and efficiency of Split in conserving memory usage for resource-constrained provers as long as the circuit can be partitioned to a Good Split, indicating that via Split zk-SNARKs can be brought one step closer to practical applications.

关键词： memory management Central Processing Unit Security optimization Privacy Authentication Smart phones memory optimization privacy zero-knowledge proof zk-SNARKs

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GEMO: Grammatical Evolution memory optimization System 12th

GEMO: Grammatical Evolution Memory Optimization System

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12th International Joint Conference on Computational Intelligence (IJCCI) / 12th International Conference on Evolutionary Computation Theory and Applications (ECTA)

作者： Kshirsagar, Meghana Jachak, Rushikesh Chaudhari, Purva Ryan, Conor Univ Limerick Biocomp Dev Syst Limerick Ireland Govt Coll Engn Dept Comp Sci Aurangabad Maharashtra India

ISBN: (纸本)9789897584756

In Grammatical Evolution (GE) individuals occupy more space than required, that is, the Actual Length of the individuals is longer than their Effective Length. This has major implications for scaling GE to complex problems that demand larger populations and complex individuals. We show how these two lengths vary for different sizes of population, demonstrating that Effective Length is relatively independent of population size, but that the Actual Length is proportional to it. We introduce Grammatical Evolution memory optimization (GEMO), a two-stage evolutionary system that uses a multi-objective approach to identify the optimal, or at least, near-optimal, genome length for the problem being examined. It uses a single run with a multi-objective fitness function defined to minimize the error for the problem being tackled along with maximizing the ratio of Effective to Actual Genome Length leading to better utilization of memory and hence, computational speedup. Then, in Stage 2, standard GE runs are performed restricting the genome length to the length obtained in Stage 1. We demonstrate this technique on different problem domains and show that in all cases, GEMO produces individuals with the same fitness as standard GE but significantly improves memory usage and reduces computation time.

关键词： Evolutionary Computation memory optimization Grammatical Evolution Multi-Objective optimization Autoregressive Time Series Forecasting

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Automatic code generation from UML for data memory optimization in microcontrollers 38

Automatic code generation from UML for data memory optimizat...

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38th Conference on Design of Circuits and Integrated Systems (DCIS)

作者： Posadas, Hector Vazquez, Jose Luis Villar, Eugenio Univ Cantabria Microelect Engn Grp Santander Spain

ISBN: (纸本)9798350303858

Design of applications for microcontrollers is typically constrained by the limited hardware capabilities of this devices. As embedded systems, the specificities of each application should be analyzed to overcome these limitations, but this is not easy to do. To help in this process, this paper proposes an analysis of some communication semantics, its potential impact on data memory usage and alternatives to minimize it. Moreover, a design tool capable of automatically generate code for microcontrollers from UML models is proposed. That way, engineers can automatically generate implementations from the communication semantics specified in the UML model. That way, exploration of the design alternatives can be done with minimal recoding effort.

关键词： microcontrollers communication semantics UML memory optimization

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Virtual memory optimization Techniques in Cloud Computing 3

Virtual Memory Optimization Techniques in Cloud Computing

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3rd IEEE International Conference on Research in Intelligent and Computing in Engineering (RICE)

作者： Deshmukh, Pranjali P. Amdani, S. Y. Prof Ram Meghe Inst Technol & Res Dept Informat Technol Badnera India Babasaheb Naik Coll Engn Dept Comp Sci & Engn Pusad India

ISBN: (纸本)9781538625996

Use of computer resources and sharing of contents has changed the ways along with as the cloud computing comes. One of the important concept of cloud computing is virtualization that plays a vital role to maximize resource usage among large number of users. To efficiently utilize the resources in a virtualized environment;they need to be over committed. Over commitment is the process of allocating more resources to a virtual machine that is physically present on the host. It is based on the principle that the majority of the Virtual Machines will use only a small percentage of the resources allocated to them at a given time. With the virtualization it becomes possible to use all different resources in shared manner and at same time by different time. There are lots of techniques now days are available to make the cloud system to be work more efficiently. This paper performs study of different changes and techniques for memory optimization and management.

关键词： Ballooning Cloud computing memory optimization Virtual Machines Virtualization VMware

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