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检索条件"主题词=Memory Optimization"

共 170 条记录，以下是11-20 订阅

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A Framework for Automatic Parallelization, Static and Dynamic memory optimization in MPSoC Platforms 10

A Framework for Automatic Parallelization, Static and Dynami...

引用

47th Design Automation Conference (DAC)

作者： Iosifidis, Yiannis Mallik, Arindam Mamagkakis, Stylianos De Greef, Eddy Bartzas, Alexandros Soudris, Dimitrios Catthoor, Francky Natl Tech Univ Athens Sch Elect & Comp Engn Athens Greece IMEC VZW Leuven Belgium

ISBN: (纸本)9781450300025

The key characteristic of next generation embedded applications will be the intensive data transfer and storage and the need for efficient memory management. The embedded system designer community needs optimization methodologies and techniques, which do not change the input-output functionality of the software applications or the design of the underlying hardware platform. In this paper, the key focus is the efficient data access and memory storage of both dynamically and statically allocated data and their assignment on the data memory hierarchy of an MPSoC platform. We propose a design tool framework to efficiently automate the time-consuming optimizations for parallelization and memory mapping of static and dynamic data for MPSoCs.

关键词： Embedded Systems MPSoC memory optimization

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Evaluation of memory optimization in a Large-scale Structural Finite Element Pre-processor 8

Evaluation of Memory Optimization in a Large-scale Structura...

引用

8th IEEE International Symposium on Embedded Multicore/Manycore Systems-on-Chip (MCSoC)

作者： Wang, Hui Lv, Ping State Nucl Power Res Inst State Nucl Power Technol Res & Dev Ctr Beijing 102209 Peoples R China

ISBN: (纸本)9781479943050

As one of important tools in the analysis of the design of nuclear power plants, finite element analysis methods have been widely used in the reactor structural analysis. ATLAS is a program for rapid analysis of finite elements of large-scale structures developed to analyze complex structures in nuclear engineering. ATLAS pre-processor has the basic realization of various functions of finite element pre-processor, the functions of importing geometry, meshing, etc. To avoid frequent system calls which can cause performance degradation, the memory pool algorithms are implemented to reduce memory fragmentations, especially for the large units of data and node data. The simulation results indicate that the designed memory pool can improve the speed of memory allocation and release by two digits in some cases. Although, for the detailed operations and support functions, there is still a large gap between ATLAS preprocessor and commercial finite element software, with the more understanding of the complex structures in nuclear engineering, ATLAS preprocessor will be upgraded in the future.

关键词： nuclear safety large-scale structure memory optimization finite element pre-processor

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DMA Performance Analysis and Multi-core memory optimization for SWIM Benchmark on the Cell Processor

DMA Performance Analysis and Multi-core Memory Optimization ...

引用

IEEE International Symposium on Parallel and Distributed Processing with Applications

作者： Dou, Yong Deng, Lin Xu, Jinhui Zheng, Yi NUDT Natl Lab Parallel & Distributed Proc Changsha 410073 Hunan Peoples R China

ISBN: (纸本)9780769534718

The Cell processor is a typical heterogeneous multi-core processor, which owns powerful computing capability. But we are facing the challenges of 'memory wall' in developing parallel applications, such as, limited capacity of local memory, limited memory bandwidth for multi-cores and the long latency for data communication. The DMA transfer mechanism is often used to hide the long latency and improve the effective usage of memory bandwidth. In the paper, we start with a series of DMA experimental tests in the context of the Cell processor architecture, and perform mathematical analysis to setup a unified formula on the average bandwidth of DMA by means of exponential fitting, which describes that SPE amount and DMA block size take main effects on DMA bandwidth in quantity. With the supports of the DMA performance formula, we perform 4 types of memory optimization in the process of parallelizing, the SWIM benchmark program into a multi-core version. We take Sony PlayStation 3 (PS3) as our test-bed. For SWIM benchmark, with 6 SPE cores, we obtain over 13 times of speedup compared to single PPE, and 3.3 to 6.18 times to AMD and Intel CPU.

关键词： DMA performance SPEC parallelization memory optimization multi-core processor Multi-core processors memory bandwidth Local memory PROCESSOR

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MAFF: Self-adaptive memory optimization for Serverless Functions 9th

MAFF: Self-adaptive Memory Optimization for Serverless Funct...

引用

9th IFIP WG 6.12 European Conference on Service-Oriented and Cloud Computing (ESOCC)

作者： Zubko, Tetiana Jindal, Anshul Chadha, Mohak Gerndt, Michael Tech Univ Munich Chair Comp Architecture & Parallel Syst Garching Germany

ISBN: (纸本)9783031047183;9783031047176

Function-as-a-Service (FaaS), a key enabler of serverless computing, has been proliferating, as it offers a cheap alternative for application development and deployment. However, while offering many advantages, FaaS also poses new challenges. In particular, most commercial FaaS providers still require users to manually configure the memory allocated to the FaaS functions based on their experience and knowledge. This often leads to suboptimal function performance and higher execution costs. In this paper, we present a framework called MAFF that automatically finds the optimal memory configurations for the FaaS functions based on two optimization objectives: cost-only and balanced (balance between cost and execution duration). Furthermore, MAFF self-adapts the memory configurations for the FaaS functions based on the changing function inputs or other requirements, such as an increase in the number of requests. Moreover, we propose and implement different optimization algorithms for different objectives. We demonstrate the functionality of MAFF on AWS Lambda by testing on four different categories of FaaS functions. Our results show that the suggested memory configurations with the Linear algorithm achieve 90% accuracy with a speedup of 2x compared to the other algorithms. Finally, we compare MAFF with two popular memory optimization tools provided by AWS, i.e., AWS Compute Optimizer and AWS Lambda Power Tuning, and demonstrate how our framework overcomes their limitations.

关键词： serverless cost optimization memory optimization duration optimization Function-as-a-Service memory allocation

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SLAM: SLO-Aware memory optimization for Serverless Applications 15

SLAM: SLO-Aware Memory Optimization for Serverless Applicati...

引用

15th IEEE International Conference on Cloud Computing (IEEE CLOUD) / IEEE World Congress on Services (IEEE SERVICES)

作者： Safaryan, Gor Jindal, Anshul Chadha, Mohak Gerndt, Michael Tech Univ Munich Chair Comp Architecture & Parallel Syst Garching Germany

ISBN: (数字)9781665481373

ISBN: (纸本)9781665481373

Serverless computing paradigm has become more ingrained into the industry, as it offers a cheap alternative for application development and deployment. This new paradigm has also created new kinds of problems for the developer, who needs to tune memory configurations for balancing cost and performance. Many researchers have addressed the issue of minimizing cost and meeting Service Level Objective (SLO) requirements for a single FaaS function, but there has been a gap for solving the same problem for an application consisting of many FaaS functions, creating complex application workflows. In this work, we designed a tool called SLAM to address the issue. SLAM uses distributed tracing to detect the relationship among the FaaS functions within a serverless application. By modeling each of them, it estimates the execution time for the application at different memory configurations. Using these estimations, SLAM determines the optimal memory configuration for the given serverless application based on the specified SLO requirements and user-specified objectives (minimum cost or minimum execution time). We demonstrate the functionality of SLAM on AWS Lambda by testing on four applications. Our results show that the suggested memory configurations guarantee that more than 95% of requests are completed within the predefined SLOs.

关键词： serverless cost optimization memory optimization SLO

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Multilayer Processing Architecture of RAM Based Neural Network with memory optimization for Navigation System

Multilayer Processing Architecture of RAM Based Neural Netwo...

引用

Joint International Conference on Rural Information and Communication Technology and Electric-Vehicle Technology (rICT and ICEV-T)

作者： Zarkasi, Ahmad Wuryandari, Aciek Ida Fauzian, Rizki Sriwijaya Univ Fac Comp Sci Study Program Comp Syst Oi 30662 South Sumatera Indonesia Bandung Inst Technol Sch Elect Engn & Informat Bandung 40132 Indonesia

ISBN: (纸本)9781479933655

Robots also have been trusted to help human to complete difficult jobs, for example, finding for the earthquake, a fire, or a sinking ship victims. The robot must be reliable, clever and moving automatically. The aim of this study is to develop and apply the application of artificial RAM-based neural networks (WNNs) on a mobile robot using a multilayer processing architecture with memory optimizations on to address and input pattern, so that producing smart navigation model which it has a simpler computational load and faster execution time. The gained result from the first study was the percentage of memory optimization in the amount of 50%. This result obtained from the formerly RAM using 8 bit data width has been optimized to 4 bits. Both of the percentage of data optimization pattern is 93.75%. This percentage is obtained from the optimization pattern (pattern taken is 4 bits MSB), each 1 bit data can handle 15 unseen patterns

关键词： RAM based neural network mobile robot multilayer processing memory optimization

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Survey of memory optimization techniques for embedded systems

Survey of memory optimization techniques for embedded system...

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3rd Brazilian Symposium on Computing Systems Engineering (SBESC)

作者： Oliveira, Lizandro Mattos, Julio C. B. Brisolara, Lisane Fed Univ Pelotas UFPel Grp Architectures & Integrated Circuits GACI Pelotas Brazil

ISBN: (纸本)9781479938902

memory systems have been pointed out as a main source to the performance and power consumption of embedded software. Embedded systems require low-power consumption, so becomes interesting investigate memory optimization techniques for these systems. There are many techniques in the literature to reduce power/energy consumption and execution time of embedded systems. This work revises and discusses these techniques focusing on hardware and software optimizations.

关键词： embedded systems memory optimization low power architecture exploration code transformation

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A memory optimization Technique for Software-Managed Scratchpad memory in GPUs

A Memory Optimization Technique for Software-Managed Scratch...

引用

IEEE 7th Symposium on Application Specific Processors

作者： Moazeni, Maryam Bui, Alex Sarrafzadeh, Majid Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90024 USA Univ Calif Los Angeles Dept Radiol Sci Los Angeles CA 90024 USA

ISBN: (纸本)9781424449392

With the appearance of massively parallel and inexpensive platforms such as the G80 generation of NVIDIA GPUs, more real-life applications will be designed or ported to these platforms. This requires structured transformation methods that remove existing application bottlenecks in these platforms. Balancing the usage of on-chip resources, used for improving the application performance, in these platforms is often non-intuitive and some applications will run into resource limits. In this paper, we present a memory optimization technique for the soft-ware-man aged scratchpad memory in the G80 architecture to alleviate the constraints of using the scratchpad memory. We propose a memory optimization scheme that minimizes the usage of memory space by discovering the chances of memory reuse with the goal of maximizing the application performance. Our solution is based on graph coloring. We evaluated our memory optimization scheme by a set of experiments on an image processing benchmark suite in medical imaging domain using NVIDIA Quadro FX 5600 and CUDA. Implementations based on our proposed memory optimization scheme showed up to 37% decrease in execution time comparing to their naive GPU implementations.

关键词： GPU Computing memory optimization CUDA

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Evaluation of the Huffman encoding for memory optimization on hardware network intrusion detection

Evaluation of the Huffman encoding for memory optimization o...

引用

3rd Brazilian Symposium on Computing Systems Engineering (SBESC)

作者： Freire, Eder Schnitman, Leizer Oliveira, Wagner Duarte, Angelo Fed Univ Bahia UFBA Polytech Sch Salvador BA Brazil State Univ Feira de Santana UEFS Dept Technol Feira De Santana BA Brazil

ISBN: (纸本)9781479938902

The design of specialized hardware for Network Intrusion Detection has been subject of intense research over the last decade due to its considerably higher performance compared to software implementations. In this context, one of the limiting factors is the finite amount of memory resources versus the increasing number of threat patterns to be analyzed. This paper proposes an architecture based on the Huffman algorithm for encoding, storage and decoding of these patterns in order to optimize such resources. We have made tests with simulation and synthesis in FPGA of rule subsets of the Snort software, and analysis indicate a saving of up to 73 percent of the embedded memory resources of the chip.

关键词： network intrusion detection FPGA memory optimization Huffman encoding

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Long Sequence Inference and memory optimization in FastFold 24

Long Sequence Inference and Memory Optimization in FastFold

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International Conference on Computer and Multimedia Technology (ICCMT)

作者： Liang, Qingfeng Wang, Zheqi Zhu, Wenwen Liu, Dong Cao, Wudi Zhengzhou Univ Sch Comp & Artificial Intelligence Zhengzhou 450000 Peoples R China Dawning Informat Ind Beijing Co Ltd Qingdao 266000 Peoples R China Dawning Informat Ind Beijing Co Ltd Nanjing 210000 Peoples R China Dawning Informat Ind Beijing Co Ltd Xian 710000 Peoples R China

ISBN: (纸本)9798400718267

AlphaFold2 has successfully solved the protein structure prediction problem that has perplexed the field of biology for 50 years, significantly reducing the prediction cost compared to traditional experimental methods. AlphaFold2 exhibits high memory demands. FastFold, a PyTorch implementation of AlphaFold2, introduced methods like Dynamic Axis Parallelism to achieve parallelism. FastFold reduces the inference time, but there is still room for memory optimization. This study explores various memory optimization techniques built upon the FastFold to reduce the model's memory requirements. The optimization methods encompass strategies such as memory fragment management, memory offloading and chunk-based computation. The optimized model maintains excellent inference capability and accuracy on GPUs with limited memory, and its maximum inference length is doubled. Using 4 GPU-like accelerators(16GB) enables the inference of proteins up to a maximum length of 3072, whereas using 8 accelerators extends the inferable length to 3511.

关键词： FastFold distributed computing deep learning memory optimization

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