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47th Design Automation Conference (DAC)

作者： Iosifidis, Yiannis Mallik, Arindam Mamagkakis, Stylianos De Greef, Eddy Bartzas, Alexandros Soudris, Dimitrios Catthoor, Francky Natl Tech Univ Athens Sch Elect & Comp Engn Athens Greece IMEC VZW Leuven Belgium

ISBN: (纸本)9781450300025

The key characteristic of next generation embedded applications will be the intensive data transfer and storage and the need for efficient memory management. The embedded system designer community needs optimization methodologies and techniques, which do not change the input-output functionality of the software applications or the design of the underlying hardware platform. In this paper, the key focus is the efficient data access and memory storage of both dynamically and statically allocated data and their assignment on the data memory hierarchy of an MPSoC platform. We propose a design tool framework to efficiently automate the time-consuming optimizations for parallelization and memory mapping of static and dynamic data for MPSoCs.

关键词： Embedded Systems MPSoC memory optimization

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MAFF: Self-adaptive memory optimization for Serverless Functions 9th

MAFF: Self-adaptive Memory Optimization for Serverless Funct...

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9th IFIP WG 6.12 European Conference on Service-Oriented and Cloud Computing (ESOCC)

作者： Zubko, Tetiana Jindal, Anshul Chadha, Mohak Gerndt, Michael Tech Univ Munich Chair Comp Architecture & Parallel Syst Garching Germany

ISBN: (纸本)9783031047183;9783031047176

Function-as-a-Service (FaaS), a key enabler of serverless computing, has been proliferating, as it offers a cheap alternative for application development and deployment. However, while offering many advantages, FaaS also poses new challenges. In particular, most commercial FaaS providers still require users to manually configure the memory allocated to the FaaS functions based on their experience and knowledge. This often leads to suboptimal function performance and higher execution costs. In this paper, we present a framework called MAFF that automatically finds the optimal memory configurations for the FaaS functions based on two optimization objectives: cost-only and balanced (balance between cost and execution duration). Furthermore, MAFF self-adapts the memory configurations for the FaaS functions based on the changing function inputs or other requirements, such as an increase in the number of requests. Moreover, we propose and implement different optimization algorithms for different objectives. We demonstrate the functionality of MAFF on AWS Lambda by testing on four different categories of FaaS functions. Our results show that the suggested memory configurations with the Linear algorithm achieve 90% accuracy with a speedup of 2x compared to the other algorithms. Finally, we compare MAFF with two popular memory optimization tools provided by AWS, i.e., AWS Compute Optimizer and AWS Lambda Power Tuning, and demonstrate how our framework overcomes their limitations.

关键词： serverless cost optimization memory optimization duration optimization Function-as-a-Service memory allocation

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DATA memory optimization IN LTE DOWNLINK

DATA MEMORY OPTIMIZATION IN LTE DOWNLINK

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IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Sharma, Namita Aa, Tom Vander Agrawal, Prashant Raghavan, Praveen Panda, Preeti Ranjan Catthoor, Francky Indian Inst Technol Delhi New Delhi India IMEC Leuven Belgium

ISBN: (纸本)9781479903566

optimizations related to memory accesses and data storage make a significant difference to the performance and energy of a wide range of data-intensive applications. Such strategies need to evolve with modern SoC and processor architectures, which lead to new optimization opportunities. In this paper, we focus on data memory optimization for LTE downlink receiver as this is a data-and computation-intensive part of the LTE application with tight energy and latency constraints. We study the data dependencies globally and conclude that by providing data samples from the antennas in interleaved form at the FFT input, we can achieve 7-15% reduction in memory access energy over an optimized implementation without any performance overhead.

关键词： Data Layout memory optimization LTE

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Design and memory optimization of motion estimation module for H.264/AVC encoder

Design and memory optimization of motion estimation module f...

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International Conference on Materials Science and Engineering Science

作者： Zhang, Duoli Wang, Chuanjie Song, Yukun Du, Gaoming Cheng, Xianwen Hefei Univ Technol Inst VLSI Design Hefei 230009 Anhui Peoples R China

ISBN: (纸本)9783037850169

H.264/AVC standard has been widely used in video compression at various kinds of application domain. Motion estimation takes the most calculation workload of H.264/AVC encoder. memory optimization has played an even more important role in encoder design. Firstly, dependency relation between motion vectors was analyzed and removed at a little cost of estimation accuracy decrement, and then a 3-stage macro-block level pipeline architecture was proposed to increase parallel process ability of motion estimation. Then an optimized memory organization strategy of reference frame data was put forward, aiming at avoiding row changing frequently in SDRAM access. Finally, based on the 3-stage pipeline structure, a shared cyclic search window memory was proposed: 1) data relativity between adjacent macro-block was analyzed, 2) and search window memory size was elaborated, 3) and then a slice based structure and the work process were discussed. Analysis and experiment result show that 50% of on chip memory resource and cycles for off chip SDRAM access can be saved. The whole design was implemented with Verilog HDL and integrated into a H.264 encoder, which can demo 1280*720@30 video successfully at frequency of 120MHz under a cyclone III FPGA development board.

关键词： memory optimization Video Compression Motion Estimation FPGA Implementation

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A memory optimization Method for High Cardinality Based on InfluxDB 24

A Memory Optimization Method for High Cardinality Based on I...

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7th International Conference on Big Data Technologies

作者： Hou, Zhuohan Huang, Qizhi Song, Yuanfeng Fan, Shuhuan Nie, Xiaowen Univ Elect Sci & Technol China Sch ISE Chengdu Sichuan Peoples R China Univ Elect Sci & Technol China Sch CSE Chengdu Sichuan Peoples R China Univ Elect Sci & Technol China Informat Ctr Chengdu Sichuan Peoples R China

ISBN: (纸本)9798400717512

The time series databases support various monitoring systems and data analysis systems. However, high cardinality may be causing memory issues. when handling a heavy workload, time series databases consume a lot of memory, resulting in a drop in read and write performance. In order to solve this problem, a memory optimization method for high cardinality based on InfluxDB is proposed. This method first reduces the number of time series data in the buffer, that is, by reducing the number of time series data decompressed by InfluxDB from the disk, thereby reducing the memory overhead required for buffering temporary data. Secondly, it delays the reading of non-essential data during the current query phase. By utilizing the data skewness between timelines, the reading of non-essential data blocks can be postponed, reducing the number of timelines present in memory at any given moment and thereby decreasing memory overhead. Experiments show that in high cardinality scenarios with a concurrency of 100,000, the optimized InfluxDB memory overhead is only 23.9% of the original InfluxDB system.

关键词： memory optimization High Cardinality Time Series Databases,InfluxDB

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memory optimization Techniques for Multithreaded Operating System on Wireless Sensor Nodes

Memory Optimization Techniques for Multithreaded Operating S...

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2014 IEEE International Conference on Progress in Informatics and Computing

作者： Xing Liu Kun Mean Hou Christophe de Vaulx Hailun Zhu Xin Liu LIMOS Laboratory UMR 6158 CNRS Blaise Pascal University Electronic Information School Wuhan University

Multithreaded operating system(OS) is essential tobe used for many wireless sensor network(WSN) applications. However, the RAM consumption of the multithreaded OS is high. Thus, itis infeasible toapply the multithreaded OS on many high RAM constrained wireless sensor nodes(WNs). Toaddress this challenge, several memory optimization strategies are investigated in this paper. On one hand, the subfunctiongranularity thread switch and hybrid OS scheduling model are proposed todecrease the RAM consumption of the thread stacks. On the other hand, different dynamic memory allocation mechanisms are presented toreduce the heap memory size. With the implementation of these optimization techniques, the total RAM consumption of the multithreaded WSN OSs can be brought down greatly. In result, the multithreaded WSN OSs become suitable tobe used even on the high RAM constrained WNs.

关键词： memory optimization dynamic memory allocation hybrid operating system wireless sensor network

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memory optimization in single chip network switch fabrics 02

Memory optimization in single chip network switch fabrics

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Proceedings of the 39th annual Design Automation Conference

作者： David Whelihan Herman Schmit Carnegie Mellon University Pittsburgh PA

ISBN: (纸本)9781581134612

Moving high bandwidth (10Gb/s+) network switches from the large scale, rack mount design space to the single chip design space requires a re-evaluation of the overall design requirements. In this paper, we explore the design space for these single chip devices by evaluating the ITRS. We find that unlike ten years ago when interconnect was scarce, the limiting factor in today's designs is on-chip memory. We then discuss an architectural technique for maximizing the effectiveness of queue memory in a single chip switch. Next, we show simulation results that indicate that a more than two order of magnitude improvement in dropped packet probability can be achieved by re-distributing memory and allowing sharing between the switch's ports. Finally, we evaluate the cost of the optimized architecture in terms of other on-chip resources.

关键词： SOC network switch memory optimization

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SPATIALLY SCALABLE RESOLUTION IMAGE CODING METHOD WITH memory optimization BASED ON WAVELET TRANSFORM

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Journal of Electronics(China) 2005年第1期22卷 94-97页

作者： WangNa ZhangLi ZhouXiao＇an JiaChuanying LiXia FacultyofInformationEng. ShenzhenUniversityShenzhen518060China TheLaboflnfo.Eng.andControls DalianMaritimeUniversityDalian116026China

This letter exploits fundamental characteristics of a wavelet transform image to form a progressive octave-based spatial resolution. Each wavelet subband is coded based on zeroblock and quardtree partitioning ordering scheme with memory optimization technique. The method proposed in this letter is of low complexity and efficient for Internet plug-in software.

关键词： memory optimization Spatially resolution scalability Wavelet transform Quard-tree partitioning

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Convolutional Neural Networks Inference memory optimization with Receptive Field-Based Input Tiling

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APSIPA TRANSACTIONS ON SIGNAL AND INFORMATION PROCESSING 2023年第1期12卷

作者： Zhuang, Weihao Hascoet, Tristan Chen, Xunquan Takashima, Ryoichi Takiguchi, Tetsuya Ariki, Yasuo Kobe Univ Kobe Hyogo 6578501 Japan

Currently, deep learning plays an indispensable role in many fields, including computer vision, natural language processing, and speech recognition. Convolutional Neural Networks (CNNs) have demonstrated excellent performance in computer vision tasks thanks to their powerful feature-extraction capability. However, as the larger models have shown higher accuracy, recent developments have led to state-of-the-art CNN models with increasing resource consumption. This paper investigates a conceptual approach to reduce the memory consumption of CNN inference. Our method consists of processing the input image in a sequence of carefully designed tiles within the lower subnetwork of the CNN, so as to minimize its peak memory consumption, while keeping the end-to-end computation unchanged. This method introduces a trade-off between memory consumption and computations, which is particularly suitable for high-resolution inputs. Our experimental results show that MobileNetV2 memory consumption can be reduced by up to 5.3 times with our proposed method. For ResNet50, one of the most commonly used CNN models in computer vision tasks, memory can be optimized by up to 2.3 times.

关键词： Convolutional neural network memory optimization receptive field

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DATA memory optimization IN LTE DOWNLINK

DATA MEMORY OPTIMIZATION IN LTE DOWNLINK

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IEEE International Conference on Acoustics, Speech, and Signal Processing

作者： Namita Sharma Tom Vander Aa Prashant Agrawal Praveen Raghavan Preeti Ranjan Panda Francky Catthoor Indian Institute of Technology Delhi New Delhi India IMEC Leuven Belgium

ISBN: (纸本)9781479903573

optimizations related to memory accesses and data storage make a significant difference to the performance and energy of a wide range of data-intensive applications. Such strategies need to evolve with modern SoC and processor architectures, which lead to new optimization opportunities. In this paper, we focus on data memory optimization for LTE downlink receiver as this is a data- and computation-intensive part of the LTE application with tight energy and latency constraints. We study the data dependencies globally and conclude that by providing data samples from the antennas in interleaved form at the FFT input, we can achieve 7-15% reduction in memory access energy over an optimized implementation without any performance overhead.

关键词： Data Layout memory optimization LTE Local thermodynamic equilibrium Long Term Evolution Range of a function memory Processor Architectures data dependency Data sampling Data Storage Fast Fourier transform ANTENNA

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