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Olfactory host finding, intermediate memory and its potential ecological adaptation in Nasonia vitripennis

NATURWISSENSCHAFTEN 2009年第3期96卷 383-391页

作者： Schurmann, Daria Collatz, Jana Hagenbucher, Steffen Ruther, Joachim Steidle, Johannes L. M. Univ Hohenheim Inst Zool Fachgebiet Tierokol D-70593 Stuttgart Germany Free Univ Berlin Inst Biol D-12163 Berlin Germany

Associative learning of host-associated chemical cues was studied in Nasonia vitripennis, a parasitoid of fly pupae in nests of hole-nesting birds. When females encountered a fly pupa and performed one sequence of host recognition behaviour including drilling the ovipositor into the host in the presence of the artificial odour furfurylheptanoate (FFH), they were afterwards arrested by FFH in olfactometer experiments. The response vanished after 4 days and could be blocked after 3 days by feeding wasps with ethacrynic acid prior and after the training. This indicates the formation of an intermediate form of memory by one host experience in N. vitripennis. Interestingly, the trained wasps avoided odours that were not present during the host encounter, although naive wasps did not react to these odours. This unique behaviour probably causes wasps to focus during host searching on those chemical cues they have experienced in the host environment. Studies in nests of hole-nesting birds revealed that about 30% of all nests contained only one fly pupa, and laboratory studies showed that N. vitripennis females are able to parasitise around 100 fly pupae in their life. It is discussed that under these conditions, the formation of a non-permanent intermediate memory for host-associated odours after one host encounter is adaptive to avoid costs involved with formation and maintenance of memory for misleading cues. The demonstration of associative olfactory learning in N. vitripennis, the first parasitoid species with sequenced genome, opens the gate to study molecular mechanisms of memory formation and its ecological adaptation in parasitoids.

关键词： Learning memory structure Parasitoid Patch size Avoidance behaviour

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Future directions for examining semantic memory in schizophrenia spectrum disorders

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CLINICAL EEG AND NEUROSCIENCE 2008年第2期39卷 95-98页

作者： Niznikiewicz, M. Boston VA Healthcare Syst Brockton MA 02301 USA Harvard Univ Sch Med Cambridge MA 02138 USA

Language abnormalities in schizophrenia are regarded as a hallmark of the disease. Clinical investigations provided accurate descriptions of the different manifestations of abnormal language use, and behavioral studies suggested several mechanisms that might contribute to these abnormalities. This review focuses on semantic memory dysfunction and, primarily, on functional methodologies such as ERP and fMRI that provide more direct measures of abnormal neural mechanisms related to language use in schizophrenia. In addition, the review points to future directions of study of the areas that received little attention thus far and whose investigation might contribute to a more detailed understanding of semantic memory dysfunction in schizophrenia.

关键词： event-related potential language memory structure schizophrenia semantic networks

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LDPC Codes for memory Systems with Scrubbing

LDPC Codes for Memory Systems with Scrubbing

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IEEE Global Telecommunications Conference (GLOBECOM 2010)

作者： Jeon, Seungjune Hwang, Euiseok Kumar, B. V. K. Vijaya Cheng, Michael K. Carnegie Mellon Univ Ctr Data Storage Syst Pittsburgh PA 15213 USA CALTECH Jet Prop Lab Pasadena CA 91109 USA

ISBN: (纸本)9781424456383

In space, radiation particles can introduce temporary or permanent errors in memory systems. To protect against potential memory faults, either thick shielding or error correcting codes (ECC) are used. Thick shielding translates into increased mass and conventional ECCs designed for memories are typically capable of only correcting a single error and detecting a double error. Decoding is usually performed through hard-decisions where bits are treated as either correct or flipped in polarity. In this work, we demonstrate that low-density parity-check (LDPC) codes that are already prevalent in many communication applications can also be used to protect memories in space. We develop a channel that models memory error events in a space radiation environment. We describe how to compute soft symbol reliabilities on our channel and compare the performance of soft-decision decoding LDPC codes against conventional hard-decision decoding of Reed-Solomon (RS) codes and Bose-Chaudhuri-Hoquenghem (BCH) codes for a specific memory structure.

关键词： Bose-Chaudhuri-Hoquenghem codes ECC Reed-Solomon codes channel coding decoding error correction codes hard-decision decoding low-density parity-check codes memory error event model memory faults memory structure memory systems parity check codes soft symb

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Exploiting memory-Level Parallelism in Reconfigurable Accelerators

Exploiting Memory-Level Parallelism in Reconfigurable Accele...

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20th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Cheng, Shaoyi Lin, Mingjie Liu, Hao Jun Scott, Simon Wawrzynek, John Univ Calif Berkeley EECS Berkeley CA 94720 USA Univ Cent Florida EECS Orlando FL 32816 USA

ISBN: (纸本)9780769546995

As memory accesses increasingly limit the overall performance of reconfigurable accelerators, it is important for high level synthesis (HLS) flows to discover and exploit memory-level parallelism. This paper develops 1) a framework where parallelism between memory accesses can be revealed from runtime profile of applications and provided to a high level synthesis flow, and 2) a novel multi-accelerator/multi-cache architecture to support parallel memory accesses, taking advantage of the high aggregated memory bandwidth found in modern FPGA devices. Our experimental results have shown that for 10 accelerators generated from 9 benchmark applications, circuits using our proposed memory structure achieve on average 52% improved performance over accelerators using a traditional memory interface. We believe that our study represents a solid advance towards achieving memory-parallel embedded computing on hybrid CPU+ FPGA platforms.

关键词： memory-Level Parallelism Application-Specific FPGA Reconfigurable memory structure High-level synthesis

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VISUALIZATION OF memory MAP INFORMATION IN EMBEDDED SYSTEM DESIGN 21

VISUALIZATION OF MEMORY MAP INFORMATION IN EMBEDDED SYSTEM D...

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21st Euromicro Conference on Digital System Design (DSD)

作者： Teuho, Mikko Pekkarinen, Esko Hamalainen, Timo D. Tampere Univ Technol Lab Pervas Comp Tampere Finland

ISBN: (纸本)9781538673768

Data compression is a common requirement for displaying large amounts of information. The goal is to reduce visual clutter. The approach given in this paper uses an analysis of a data set to construct a visual representation. The visualization is compressed using the address ranges of the memory structure. This method produces a compressed version of the initial visualization, retaining the same information as the original. The presented method has been implemented as a memory Designer tool for ASIC, FPGA and embedded systems using IP-XACT. The memory Designer is a user-friendly tool for model based embedded system design, providing access and adjustment of the memory layout from a single view, complementing the "programmer's view" to the system.

关键词： data visualization display space compression filtering memory structure

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Energy-Efficient Non-Volatile TCAM Search Engine Design Using Priority-Decision in memory Technology for DPI 15

Energy-Efficient Non-Volatile TCAM Search Engine Design Usin...

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52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

作者： Tsai, Hsiang-Jen Yang, Keng-Hao Peng, Yin-Chi Lin, Chien-Chen Tsao, Ya-Han Chang, Meng-Fan Chen, Tien-Fu Natl Chiao Tung Univ Dept CS Hsinchu Taiwan Natl Tsing Hua Univ Dept EE Hsinchu Taiwan

ISBN: (纸本)9781450335201

TCAM-based search engines are widely used in regular expression matching across multiple packets. However, the use of priority encoder results in increased energy consumption of pattern updates and search operations. This work, proposes a promising memory technology, called Priority-Decision in memory (PDM), which eliminates the need for priority encoders and removes restrictions on ordering, meaning that patterns can be stored in an arbitrary order without sorting their lengths. Moreover, we present a Sequential Input-State Search (SIS) scheme to disable the mass of redundant search operations in state segments, based on the analysis distribution of hex signatures in a virus database. Experimental results demonstrate that PDM-based technology can improve update energy consumption of nvTCAM search engines by 36%similar to 67% because most of the energy in the latter is used to reorder. By adopting the SIS-based method to avoid unnecessarily search operations in a TCAM array, the search energy reduction is around 64% of nvTCAM search engines.

关键词： Priority-decision in memory Non-volatile TCAM search engine architecture memory structure Deep packet inspection

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A New Approach to Malware Detection by Comparative Analysis of Data structures in a memory Image

A New Approach to Malware Detection by Comparative Analysis ...

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International Congress on Technology, Communication and Knowledge (ICTCK)

作者： Aghaeikheirabady, Masoume Farshchi, Seyyed Mohammad Reza Shirazi, Hossein MalekAshtar Univ Dept Informat Technol & Commun Secur Tehran Iran Ferdowsi Univ Mashhad Mashhad Iran

ISBN: (纸本)9781479980215

Physical memory forensics has grown in popularity in recent years. Since malware typically operate in user space, it is important to reconstruct and track their process behavior. This paper focuses on detecting malware through a comparison of the information in the user space memory data structures. In order to expedite information extraction and ensure accuracy, the data in multiple memory management structures in the user space and the kernel are used concurrently. In the proposed method, using descriptions of memory structures, weextractmalware artifactsrelated to registry changes as well as, calls to library files and operating system functions. The extracted features are then evaluated, and samples are classified according to the selected attributes. The best results include a 98% detection rate and false positive rate of 16%, which indicates the effectiveness of the proposed behavior extraction method.

关键词： data structures digital forensics feature extraction invasive software storage management behavior extraction method comparative analysis detection rate false positive rate information extraction library files malware artifact malware detection memory image memory structure multiple memory management structure operating system function physical memory forensic user space memory data structure Computers Data mining Feature extraction Forensics Kernel Malware Feature extraction Spyware Store management memory structures Invasive software Data structures E-discovery Information Extraction detection rate (DR) Computers data mining Kernel information retrieval forensic science

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A modified tabu search algorithm for cost-based job shop problem

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JOURNAL OF THE OPERATIONAL RESEARCH SOCIETY 2010年第4期61卷 611-619页

作者： Zhu, Z. C. Ng, K. M. Ong, H. L. Natl Univ Singapore Dept Ind & Syst Engn Singapore 119260 Singapore

In this paper, a cost-based job shop problem (JIT-JSP) is proposed to model the multi-order processing procedure in a just-in-time (JIT) environment. The objective of JIT-JSP is to minimize three costs: work-in-process holding cost of half-finished orders, inventory holding cost of finished orders and backorder cost of unfulfilled orders. A modified tabu search (MTS) method is developed to improve the schedule quality by searching the neighbourhood of a feasible schedule iteratively. The MTS method is comprised of three components that help to ensure a more effective searching procedure: neighbourhood structure, memory structure and filter structure. Computational results show that the MTS method significantly improves the initial schedule generated by an arbitrarily selected dispatching rule. Journal of the Operational Research Society (2010) 61, 611-619. doi: 10.1057/jors.2009.9 Published online 18 March 2009

关键词： job shop problem cost-based problem tabu search neighbourhood structure memory structure filter structure

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Distributed generation, reactive sources and network-configuration planning for power and energy-loss reduction

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IEE PROCEEDINGS-GENERATION TRANSMISSION AND DISTRIBUTION 2006年第2期153卷 127-136页

作者： Golshan, MEH Arefifar, SA Isfahan Univ Technol Dept Elect & Comp Engn Esfahan Iran

Taking account of the mutual impacts of distributed generation, reactive power and network-configuration planning, a new and more comprehensive distributed-generation-planning problem including simultaneous distributed generation, reactive sources and network configuration planning is defined. By solving this problem the amount of distributed-generation resources (DGRs) kind reactive-power Sources (RPSs) in selected buses of a distribution system, are determined taking account of their Outputs at different load levels, tap positions of voltage regulators (VRs) and the status of sectionalising switches, in order to minimise the cost of power, energy losses and the total required reactive power subjected to a given total of distributed generation. Since the defined planning problem is a combinatorial one, a solution algorithm based on tabu search, that is an efficient heuristic method to a combinatorial-optimisation problem, is proposed. Various memory structures including short-, intermediate- and long-term memories have been implemented in the algorithm. The method has been tested on 33-bus and 69-bus radial distribution systems to demonstrate the performance of the algorithm and to investigate impact of some parameters such as maximum limits on size of DGRs (RPSs), constant or controllable Outputs of these sources and different control variables sets oil results of system planning. In addition, a novel technique for determining the candidate buses to install active (reactive) sources based oil clustering system buses in view of assigning DGRs (RPSs) is presented.

关键词： 69-bus radial distribution system distributed power generation optimisation memory structure Combinatorial mathematics energy-loss reduction Optimisation techniques power distribution control heuristic method Distribution networks search problems reactive power Power system control network-configuration planning 33-bus radial distribution system power loss reduction tabu search power cost combinatorial mathematics Control of electric power systems Power system planning and layout voltage regulators Voltage control power distribution planning voltage regulator distributed generation losses combinatorial-optimisation problem system bus

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Emerging Nanodevice Paradigm: Graphene-Based Electronics for Nanoscale Computing

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ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS 2009年第1期5卷 1–19页

作者： Wang, Z. F. Zheng, Huaixiu Shi, Q. W. Chen, Jie Hefei Natl Lab Phys Sci Microscale Hefei Peoples R China Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2M7 Canada

The continued miniaturization of silicon-based electronic circuits is fast approaching its physical limitations. It is unlikely that advances in miniaturization, following the so-called Moore's Law, can continue in the foreseeable future. Nanoelectronics has to go beyond silicon technology. New device paradigms based on nanoscale materials, such as molecular electronic devices, spin devices and carbon-based devices, will emerge. In this article, we introduce a nanodevice paradigm: graphene nanoelectronics. Due to its unique quantum effects and electronic properties, researchers predict that graphene-based devices may replace carbon nanotube devices and become major building blocks for future nanoscale computing. To manifest its unique electronic properties, we present some of our recent designs, namely a graphene-based switch, a negative differential resistance (NDR) device and a random access memory array (RAM). Since these basic devices are the building blocks for large-scale circuits, our findings can help researchers construct useful computing systems and study graphene-based circuit performance in the future.

关键词： Graphene device negative differential resistance memory structure tight-binding model

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