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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Xia, Kaifeng Wu, Bin Zhou, Xiaoping Xiong, Tao Chinese Acad Sci Inst Microelect Bei Jing Peoples R China

ISBN: (纸本)9781479953417

This paper presents an efficient memory-based fast Fourier transform processor including 35 different working sizes for LTE systems. A factorization method named high-radixsmall-butterfly combined with a conflict-free address scheme for 2(p)3(q)5(r) point memory-based fft processor is proposed. The processor can not only provide conflict-free concurrent data access from different memory banks but also continuous-flow working mode. Moreover, we exploit prime factor algorithm to decrease the multiplications and twiddle factor storage. In addition, a unified Winograd Fourier transform algorithm butterfly core was designed for the small 2, 3, 4, 5-point DFTs. The fft processor was implemented in a SMIC 55nm CMOS process with core area 1:063mm(2). The chip consumes 40.8mW at 122.88MHz operating frequency with 1.08V voltage supply.

关键词： conflict-free address scheme memory-based fft processor prime factor algorithm Winograd algorithm LTE

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An efficient prime factor memory-based fft processor for LTE systems

An efficient prime factor memory-based FFT processor for LTE...

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International Symposium on Circuits and Systems

作者： Kaifeng Xia Bin Wu Xiaoping Zhou Tao Xiong Institute of Microelectronics of Chinese Academy of Sciences Bei-jing China

ISBN: (纸本)9781479953424

Abstract: This paper presents an efficient memory-based fast Fourier transform processor including 35 different working sizes for LTE systems. A factorization method named high-radix-small-butterfly combined with a conflict-free address scheme for 2~p3~q5~r point memory-based fft processor is proposed. The processor can not only provide conflict-free concurrent data access from different memory banks but also continuous-flow working mode. Moreover, we exploit prime factor algorithm to decrease the multiplications and twiddle factor storage. In addition, a unified Winograd Fourier transform algorithm butterfly core was designed for the small 2, 3, 4, 5-point DFTs. The fft processor was implemented in a SMIC 55nm CMOS process with core area 1.063mm~2. The chip consumes 40 8mW at 122.88MHz operating frequency with 1.08V voltage supply.

关键词： LTE conflict-free address scheme memory-based fft processor prime factor algorithm Winograd algorithm

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A Generalized Conflict-free Address Scheme for Arbitrary 2^k-point memory-based fft processors

A Generalized Conflict-free Address Scheme for Arbitrary 2<i...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Xia, Kaifeng Wu, Bin Zhou, Xiaoping Xiong, Tao Chinese Acad Sci Inst Microelect Beijing Peoples R China

ISBN: (纸本)9781479953417

This paper presents an efficient conflict-free memory address scheme for arbitrary 2(k)-point memory-based fft processors. The address scheme can support in-place strategy, continuous-flow mode, and variable size for arbitrary long sized fft. Moreover, the address scheme can adjust the throughput by changing the computation radix and the parallelism of the arithmetic processing units according to the specific implementation requirements. We have designed a configurable 128 - 2048 point fft processor for LTE system. From the results, we can see the proposed address scheme has excellent point flexibility, hardware efficiency, and can support almost any 2(k)-point fft implementations.

关键词： conflict-free address scheme continuous-flow in-place LTE memory-based fft processor

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Low-cost fft processor for DVB-T2 Applications

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2010年第4期56卷 2072-2079页

作者： Lin, Shin-Yo Wey, Chin-Long Shieh, Ming-Der Natl Cent Univ Dept Elect Engn Jhongli Taiwan Natl Cheng Kung Univ Dept Elect Engn Tainan 70101 Taiwan

An efficient Fast Fourier Transform (fft) processor is greatly needed for real-time operation in many OFDM applications, such as xDSL, DAB, DVB-T/H, and etc. This paper presents a low-cost Parallel memory-based fft (PMB-fft) processor for DVB-T2 applications. The processor has been designed and implemented in 90nm 1P9M CMOS process. Experimental results show that the PMB-fft processor meets the DVB-T2 standard with N=32,768 points, and takes only 2.51 mm(2) in the core area with a power consumption of 0.89 mW at 25MHz.

关键词： Fast Fourier Transform memory-based fft processor Orthogonal Frequency Division Multiplexing DVB-T2 Parallel Structure Pipeline Structure

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A generalized conflict-free address scheme for arbitrary 2k-point memory-based fft processors

A generalized conflict-free address scheme for arbitrary 2k-...

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International Symposium on Circuits and Systems

作者： Kaifeng Xia Bin Wu Xiaoping Zhou Tao Xiong Institute of Microelectronics of Chinese Academy of Sciences Bei-jing China

ISBN: (纸本)9781479953424

This paper presents an efficient conflict-free memory address scheme for arbitrary 2k-point memory-based fft processors. The address scheme can support in-place strategy, continuous-flow mode, and variable size for arbitrary long sized fft. More over, the address scheme can adjust the throughput by changing the computation radix and the parallelism of the arithmetic processing units according to the specific implementation requirements. We have designed a configurable 128 - 2048 point fft processor for LTE system. From the results, we can see the proposed address scheme has excellent point flexibility, hardware efficiency, and can support almost any 2k-point fft implementations.

关键词： memory-based fft processor conflict-free address scheme continuous-flow inplace LTE

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