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检索条件"主题词=Microcode"

共 115 条记录，以下是21-30 订阅

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A Static microcode Analysis Tool for Programmable Load Drivers 15

A Static Microcode Analysis Tool for Programmable Load Drive...

引用

15th IEEE International Working Conference on Source Code Analysis and Manipulation (SCAM)

作者： Dariz, Luca Ruggeri, Massimiliano Selvatici, Michele Italian Natl Council Res CNR Inst Agr & Earthmoving Machines IMAMOTER Via Canal Bianco 28 I-44124 Ferrara Italy

ISBN: (纸本)9781467375290

The advances in control electronics, with the introduction of programmable load drivers, have changed the way in which actuators, both resistive and inductive, such as electrical motors, injectors, valves, are controlled. However, usually the only programming language available for these drivers is the native assembly-like microcode that, allowing for unstructured programing constructs, exposes to the risk of dangerous control flow paths, like infinite loops or jumps to non-existent locations. In this paper an automatic static analyzer is presented, which reconstruct the control flow graph of an application from the microcode source file and checks for infinite loops and undefined jumps caused by the corresponding jump register not being set for a particular path.

关键词： static analysis Control Flow Graph CFG microcode power driver infinite loop

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Software-Defined CPU Modes 23

Software-Defined CPU Modes

引用

19th ACM Workshop on Hot Topics in Operating Systems (HotOS)

作者： Roitzsch, Michael Miemietz, Till von Elm, Christian Asmussen, Nils Barkhausen Inst Dresden Germany Tech Univ Dresden Dresden Germany

ISBN: (纸本)9798400701955

Our CPUs contain a compute instruction set, which regular applications use. But they also feature an intricate underworld of different CPU modes, combined with trap and exception handling to transition between these modes. These mechanisms are manifold and complex, yet the layering and functionality offered by the CPU modes is fixed. We have to take what CPU vendors provide, including potential security problems from unneeded modes. This paper explores the question, whether CPU modes could instead be defined entirely by software. We show how such a design would function and explore the advantages it enables. We believe that pushing all existing modes under a common design umbrella would enforce a cleaner structure and more control over exposed functionality. At the same time, the flexibility of software-defined modes enables interesting new use cases.

关键词： processor modes mode transitions microcode

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Dual-IS: Instruction Set Modality for Efficient Instruction Level Parallelism 35th

Dual-IS: Instruction Set Modality for Efficient Instruction ...

引用

35th International Conference on Computer Architecture (ARCS)

作者： Hepola, Kari Multanen, Joonas Jaaskelainen, Pekka Tampere Univ Tampere Finland

ISBN: (纸本)9783031218668;9783031218675

Exploiting instruction level parallelism (ILP) is a widely used method for increasing performance of processors. While traditional very long instruction word (VLIW) processors can exploit ILP energy-efficiently thanks to static instruction scheduling, they suffer from bad code density with serial parts that cannot utilize the multi-issue capabilities. Transport triggered architecture (TTA) is a variation of the VLIW paradigm with an exposed datapath that improves scaling of VLIW processors with the cost of even wider instructions by exposing the datapath interconnection network to the programmer. To this end, we propose Dual-IS, an architecture that implements a TTA multi-issue and RISC-V compatible single-issue instruction-set modes by means of a microcoded control path. By utilizing the instruction set modality, the TTA mode can be used in codes that benefit from ILP, while a single-issue RISC-V ISA mode reduces instruction stream energy and code size for sequential programs. Thanks to the TTA programming model, the static multi-issue mode can be implemented without additional register file ports. The processor was synthesized on a 28nm ASIC technology. For this design point, when instruction-set mode was selected based on energy-delay product at the program granularity, with CHStone benchmarks, Dual-IS had on average 14% lower energy-delay product compared to a single-mode TTA processor with a similar datapath, while only adding a 3% overhead in the core area. Dual-IS achieved on average 15% and in the best case 33% smaller run times than a single-issue RISC-V implementation by running programs in the TTA mode only when it was beneficial in terms of performance.

关键词： Instruction level parallelism microcode Multiple instruction set architecture Transport triggered architecture

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Flexible Instruction Set Architecture for Programmable Look-up Table based Processing-in-Memory 39

Flexible Instruction Set Architecture for Programmable Look-...

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39th IEEE International Conference on Computer Design ICCD)

作者： Connolly, Mark Sutradhar, Purab Ranjan Indovina, Mark Ganguly, Amlan Rochester Inst Technol Dept Comp Engn Rochester NY 14623 USA

ISBN: (纸本)9781665432191

Processing in Memory (PIM) is a recent novel computing paradigm that is still in its nascent stage of development. Therefore, there has been an observable lack of standardized and modular Instruction Set Architectures (ISA) for the PIM devices. In this work, we present the design of an ISA which is primarily aimed at a recent programmable Look-up Table (LUT) based PIM architecture. Our ISA performs the three major tasks of i) controlling the flow of data between the memory and the PIM units, ii) reprogramming the LUTs to perform various operations required for a particular application, and iii) executing sequential steps of operation within the PIM device. A microcoded architecture of the Controller/Sequencer unit ensures minimum circuit overhead as well as offers programmability to support any custom operation. We provide a case study of CNN inferences, large matrix multiplications, and bitwise computations on the PIM architecture equipped with our ISA and present performance evaluations based on this setup. We also compare the performances with several other PIM architectures.

关键词： Instruction set architecture microcode processing in memory look-up table convolutional neural network deep neural network DRAM

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Improving on the Experience of Hand-Assembling Programs for Application-Specific Architectures 21

Improving on the Experience of Hand-Assembling Programs for ...

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5th International Conference on the Art, Science, and Engineering of Programming (Programming)

作者： Piumarta, Ian Kyoto Univ Adv Sci Kyoto Japan

ISBN: (纸本)9781450389860

Creating an application-specific processor is an effective and popular way to solve many problems in embedded hardware design using FPGAs, ASICs, or custom silicon. Programming these processors is complicated by the lack of toolchain support for creating the necessary binary code as part of hardware design, implementation, and evaluation. Hardware developers who cannot create their own ad-hoc assembler are left to hand-assemble their code into binary instructions which is both painful and error prone. We present a tool that supports the rapid creation of assemblers for application-specific processors. A single language is used to specify both instruction formats as collections of bit fields and the instantiation of those formats into sequences of binary instructions as a single, homogeneous activity that is designed to be as familiar and accessible to hardware designers as possible. The output from the tool can be used directly by hardware synthesis tools to initialise the program memory of an application-specific processor.

关键词： domain specific languages macro languages micro assemblers microcode embedded programming application specific processor implementation FPGA configuration memory

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Mobilizing the Micro-Ops: Exploiting Context Sensitive Decoding for Security and Energy Efficiency 18

Mobilizing the Micro-Ops: Exploiting Context Sensitive Decod...

引用

45th ACM/IEEE Annual International Symposium on Computer Architecture (ISCA)

作者： Taram, Mohammadkazem Venkat, Ashish Tullsen, Dean M. Univ Calif San Diego La Jolla CA 92093 USA

ISBN: (纸本)9781538659847

Modern instruction set decoders feature translation of native instructions into internal micro-ops to simplify CPU design and improve instruction-level parallelism. However, this translation is static in most known instances. This work proposes context-sensitive decoding, a technique that enables customization of the micro-op translation at the microsecond or faster granularity, based on the current execution context and/or preset hardware events. While there are many potential applications, this work demonstrates its effectiveness with two use cases: 1) as a novel security defense to thwart instruction/data cache-based side-channel attacks, as demonstrated on commercial implementations of RSA and AES and 2) as a power management technique that performs selective devectorization to enable efficient unit-level power gating. This architecture, first by allowing execution to transition between different translation modes rapidly, defends against a variety of attacks, completely obfuscating code-dependent cache access, only sacrificing 5% in steady-state performance orders of magnitude less than prior art. By selectively disabling the vector units without disabling vector arithmetic, context sensitive decoding reduces energy by 12.9% with minimal loss in performance. Both optimizations work with no significant changes to the pipeline or the external ISA.

关键词： microcode Side Channel Security Power Gating

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Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture 16

Concurrent Dynamic Memory Coalescing on GoblinCore-64 Archit...

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International Symposium on Memory Systems (MEMSYS)

作者： Wang, Xi Leidel, John D. Chen, Yong Texas Tech Univ Whitacre Coll Engn Dept Comp Sci Box 43104 Lubbock TX 79409 USA

ISBN: (纸本)9781450343053

The majority of modern microprocessors are architected to utilize multi-level data caches as a primary optimization to reduce the latency and increase the perceived bandwidth from an application. The spatial and temporal locality provided by data caches work well in conjunction with applications that access memory in a linear fashion. However, applications that exhibit random or non-deterministic memory access patterns often induce a significant number of data cache misses, thus reducing the natural performance benefit from the data cache. In response to the performance penalties inherently present with non-deterministic applications, we have constructed a unique memory hierarchy within the GoblinCore-64 (GC64) architecture explicitly designed to exploit memory performance from irregular memory access patterns. The GC64 architecture combines a RISC-V-based core coupled with latency-hiding architectural features to a memory hierarchy with Hybrid Memory Cube (HMC) devices. In order to cope with the inherent non-determinism of applications and to exploit the packetized interface presented by the HMC device, we develop a methodology and associated implementation of a dynamic memory coalescing unit for the GC64 memory hierarchy that permits us to statistically sample memory requests from non-deterministic applications and coalesce them into the largest possible HMC payload requests. In this work, we present two parallel methodologies and associated implementations for coalescing non-deterministic memory requests into the largest potential HMC request by constructing a binary tree representation of the live memory requests from disparate cores. We present the coalesced HMC memory request results from applications that exhibit linear and non-linear memory request patterns compiled for a RISC-V core in contrast with a traditional memory hierarchy.

关键词： Memory Coalescing microcode GoblinCore-64 RISC-V Parallel Computing Data-Intensive Computing

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Dec :: Pdp11 :: 1140 :: 1140E :: a Primer on the Smile Microprogram Load and Test System Jul78

引用

2016年

[Auto Generated] Address Register Content Comment 777 700 R[O] 001036 Address of halt instruction 777 702 R[l] 1 777 704 R[2] 2 777 706 R[3] 3 777 710 R[4] 4 777 712 R[6] 132776 Stack start address 777 714 R[6] 132766 Stack pointer 777 716 R[7] 001040 Current program counter below. Address 132 776 132 774 132 772 132 770 132 766 After the following Address 777 702 777 704 777 706 777 710 Content 5 4 3 2 0 execution of values. Register R[l] R[2] R[3] R[4] 3.B Bootstrapping UNIX Comment Content of