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Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2013年第9期21卷 1756-1761页

作者： Lin, Jun Yan, Zhiyuan Lehigh Univ Dept Elect & Comp Engn Bethlehem PA 18015 USA

In this brief, a shuffled schedule (SS) of the min-max decoding algorithm is proposed for nonbinary low-density parity-check (LDPC) codes. To increase the throughput and reduce the memory requirement, a modified SS (MSS) with much simpler check node processing is also proposed, based on a new shuffled merge algorithm. Numerical simulations for three LDPC codes with different lengths and rates over GF(32) show: 1) both SS and MSS converge faster and have slightly better error performance than the flooding schedule, and 2) the degradation of the MSS in error performance as well as convergence rate is negligible. Finally, an efficient decoder architecture based on the MSS is proposed for quasi-cyclic LDPC codes. The proposed decoder architecture further enhances the decoding throughput with improved check and variable node processing units. The implementation results of an (837, 726) LDPC decoder over GF(32) demonstrate that the proposed architecture outperforms those in previous works.

关键词： min-max decoding nonbinary low-density parity-check codes shuffle decoding

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Block-Layered Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2015年第2期78卷 209-222页

作者： Choi, Chang-Seok Lee, Hanho Inha Univ Dept Informat & Commun Engn Inchon 402751 South Korea

This paper presents a block-layered decoder architecture and efficient design techniques for quasi-cyclic nonbinary low-density parity-check (QC-NB-LDPC) codes. Based on a min-max decoding algorithm, an efficient block-layered decoder architecture for QC-NB-LDPC codes is proposed for fast decoder convergence. Further, a novel two-way merging min-max algorithm, which significantly reduces decoding latency, is proposed for check node processing. The NB-LDPC decoder using the proposed algorithm can provide a considerably higher throughput rate than that using a conventional min-max algorithm. The proposed (225, 165) NB-LDPC decoder over GF(2(4)) is synthesized using a 90-nm CMOS process. It can operate at a clock rate of 400 MHz and achieve a data processing rate of 24.6 Mbps under 10 decoding iterations.

关键词： Nonbinary Low-density parity-check (LDPC) codes min-max decoding Two-way merging Block-layered VLSI

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Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2010年第5期57卷 1071-1082页

作者： Lin, Jun Sha, Jin Wang, Zhongfeng Li, Li Nanjing Univ Inst VLSI Design Dept Phys Jiangsu Prov Key Lab Adv Photon & Elect Mat Nanjing 210093 Peoples R China Broadcom Corp Irvine CA 92617 USA

This paper addresses decoder design for nonbinary quasicyclic low-density parity-check (QC-LDPC) codes. First, a novel decoding algorithm is proposed to eliminate the multiplications over Galois field for check node processing. Then, a partially parallel architecture for check node processing units and an optimized architecture for variable node processing units are developed based on the new decoding algorithm. Thereafter, an efficient decoder structure dedicated to a promising class of high-performance nonbinary QC-LDPC codes is presented for the first time. Moreover, an ASIC implementation for a (620, 310) nonbinary QC-LDPC code decoder over GF(32) is designed to demonstrate the efficiency of the presented techniques.

关键词： Decoder architecture extended min-sum (EMS) fast Fourier transform (FFT) belief propagation (BP) min-max decoding nonbinary quasicyclic low-density parity-check (QC-LDPC) codes very large scale integration (VLSI)

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Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2012年第6期59卷 381-385页

作者： He, Kai Sha, Jin Wang, Zhongfeng Nanjing Univ Inst VLSI Design Sch Elect Sci & Engn Nanjing 210093 Jiangsu Peoples R China Broadcom Corp Irvine CA 92617 USA

Nonbinary low-density parity-check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity iterative decoding algorithms have been proposed, the VLSI implementation of NB-LDPC decoders still remains a big challenge due to its high complexity and long latency. In this brief, a highly efficient check node processing scheme, which the processing delay greatly reduced, is proposed for min-max decoding algorithm. Thereafter, an efficient check node unit (CNU) can be designed. Compared with previous works, the latency of the CNU could be reduced to less than 52%. In addition, a decoder for a (620, 310) NB-LDPC code is designed to demonstrate the efficiency of the presented techniques.

关键词： Low-density parity-check (LDPC) codes min-max decoding nonbinary VLSI design

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An Efficient VLSI Architecture for Nonbinary LDPC Decoders

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2010年第1期57卷 51-55页

作者： Lin, Jun Sha, Jin Wang, Zhongfeng Li, Li Nanjing Univ Inst VLSI Design Jiangsu Prov Key Lab Adv Photon & Elect Mat Dept Phys Nanjing 210093 Peoples R China Broadcom Corp Irvine CA 92617 USA

Low-density parity-check (LDPC) codes constructed over the Galois field GF(q), which are also called nonbinary LDPC codes, are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity quasi-optimal iterative decoding algorithms have been proposed, the VLSI implementation of nonbinary LDPC decoders has rarely been discussed due to their hardware unfriendly properties. In this brief, an efficient selective computation algorithm, which totally avoids the sorting process, is proposed for min-max decoding. In addition, an efficient VLSI architecture for a nonbinary min-max decoder is presented. The synthesis results are given to demonstrate the efficiency of the proposed techniques.

关键词： Galois field min-max decoding nonbinary low-density parity-check (LDPC) codes VLSI

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