In this brief, we present a hardware efficient implementation of a threshold modified min-sum algorithm (MSA) to improve the performance of a low density parity-check (LDPC) decoder. The proposed architecture introduc...
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In this brief, we present a hardware efficient implementation of a threshold modified min-sum algorithm (MSA) to improve the performance of a low density parity-check (LDPC) decoder. The proposed architecture introduces a novel lookup table based threshold attenuation technique, called threshold attenuated MSA (TAMSA). The proposed TAMSA implementation is shown to improve bit error rate (BER) performance compared to the conventional AMSA and MSA. Furthermore, a layered version of the TAMSA implementation is investigated to reduce hardware cost. Utilizing circuit optimization techniques, including a parallel computing structure, the proposed layered TAMSA field-programmable gate array (FPGA) implementation results show that the modified architecture requires no extra circuit power or circuit area compared to conventional AMSA, and only 0.07% extra leaf cells compared to conventional MSA.
In this study, the authors present an improved min-sum (MS) algorithm based on density evolution (DE) called the DE MS algorithm for low-density parity check codes. First, they use DE theory to calculate the probabili...
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In this study, the authors present an improved min-sum (MS) algorithm based on density evolution (DE) called the DE MS algorithm for low-density parity check codes. First, they use DE theory to calculate the probability density function of the check-to-variable message of the belief propagation (BP) algorithm and the MS/normalised MS (NMS) algorithm and furthermore to calculate the normalised factor . Then, is modified further by using the weighted average. Finally, in order to ensure the decoding performance and reduce the hardware complexity, the same is used for different signal-to-noise ratios. The simulation results show that a gain of about 0.2dB can be achieved in comparison with the classical NMS algorithm. In addition, this algorithm can obtain the same decoding performance compared with the Linear minimum Mean Square Error (LMMSE) MS algorithm whose decoding performance is very close to that of the BP algorithm, and it also saves around 24.57% of logic elements and 34.33% of memory bits compared with the LMMSE MS algorithm at the same time.
In this paper, we propose a new modified normalized min-sum algorithm for low-density parity-check decoding. Instead of normalizing the results of the check node renew calculations by a single modification factor, we ...
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In this paper, we propose a new modified normalized min-sum algorithm for low-density parity-check decoding. Instead of normalizing the results of the check node renew calculations by a single modification factor, we use two different modification factors to normalize the results of check node renew calculations. One modification factor for the position of the first minimum value and another modification factor for other positions. We obtain two modification factors by theoretical analysis using the theory of order statistics. Simulation results show that the new modified normalized min-sun algorithm achieves better bit error rate performance than normalized min-sun algorithm without adding implementation complexity. Copyright (C) 2016 John Wiley & Sons, Ltd.
Low-density parity-check (LDPC) codes have attracted a great attention because of their excellent error correction capability with reasonably low decoding complexity. Among decoding algorithms for LDPC codes, the min-...
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Low-density parity-check (LDPC) codes have attracted a great attention because of their excellent error correction capability with reasonably low decoding complexity. Among decoding algorithms for LDPC codes, the min-sum (MS) algorithm and its modified versions have been widely adopted due to their high efficiency in hardware implementation. In this paper, a self-adaptive MS algorithm using the difference of the first two minima is proposed for faster decoding speed and lower power consumption. Finding the first two minima is an important operation when MS-based LDPC decoders are implemented in hardware, and the found minima are often compressed using the difference of the two values to reduce interconnection complexity and memory usage. It is found that, when these difference values are bounded, decoding is not successfully terminated. Thus, the proposed method dynamically decides whether the termination-checking step will be carried out based on the difference in the two found minima. The simulation results show that the decoding speed is improved by 7%, and the power consumption is reduced by 16.34% by skipping unnecessary steps in the unsuccessful iteration without any loss in error correction performance. In addition, the synthesis results show that the hardware overhead for the proposed method is negligible.
Among various decoding algorithms of low-density parity-check (LDPC) codes, the min-sum (MS) algorithm and its modified algorithms are widely adopted because of their computational simplicity compared to the sum-produ...
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Among various decoding algorithms of low-density parity-check (LDPC) codes, the min-sum (MS) algorithm and its modified algorithms are widely adopted because of their computational simplicity compared to the sum-product (SP) algorithm with slight loss of decoding performance. In the MS algorithm, the magnitude of the output message from a check node (CN) processing unit is decided by either the smallest or the next smallest input message which are denoted as min1 and min2, respectively. It has been shown that multiplying a scaling factor to the output of CN message will improve the decoding performance. Further, Zhong et al. have shown that multiplying different scaling factors (called a 2-dimensional scaling) to min1 and min2 much increases the performance of the LDPC decoder. In this paper, the simplified 2-dimensional scaled (S2DS) MS algorithm is proposed. In the proposed algorithm, we figure out a pair of the most efficient scaling factors which multiplications can be replaced with combinations of addition and shift operations. Furthermore, one scaling operation is approximated by the difference between min1 and min2. The simulation results show that S2DS achieves the error correcting performance which is close to or outperforms the SP algorithm regardless of coding rates, and its computational complexity is the lowest comparing to modified versions of MS algorithms.
Message-passing algorithms based on belief-propagation (BP) are successfully used in many applications, including decoding error correcting codes and solving constraint satisfaction and inference problems. The BP-base...
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Message-passing algorithms based on belief-propagation (BP) are successfully used in many applications, including decoding error correcting codes and solving constraint satisfaction and inference problems. The BP-based algorithms operate over graph representations, called factor graphs, that are used to model the input. Although in many cases, the BP-based algorithms exhibit impressive empirical results, not much has been proved when the factor graphs have cycles. This paper deals with packing and covering integer programs in which the constraint matrix is zero-one, the constraint vector is integral, and the variables are subject to box constraints. We study the performance of the min-sum algorithm when applied to the corresponding factor graph models of packing and covering linear programmings (LPs). We compare the solutions computed by the min-sum algorithm for packing and covering problems to the optimal solutions of the corresponding LP relaxations. In particular, we prove that if the LP has an optimal fractional solution, then for each fractional component, the minsumalgorithm either computes multiple solutions or the solution oscillates below and above the fraction. This implies that the min-sum algorithm computes the optimal integral solution only if the LP has a unique optimal solution that is integral. The converse is not true in general. For a special case of packing and covering problems, we prove that if the LP has a unique optimal solution that is integral and on the boundary of the box constraints, then the min-sum algorithm computes the optimal solution in pseudopolynomial time. Our results unify and extend recent results for the maximum weight matching problem and for the maximum weight independent set problem.
In 2009, the presentation of polar code, the first theory to approach the Shannon limit of communication channel coding schemes. Thus, academics and business have focused on Polar codes. Research and worldwide standar...
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ISBN:
(纸本)9798350310801
In 2009, the presentation of polar code, the first theory to approach the Shannon limit of communication channel coding schemes. Thus, academics and business have focused on Polar codes. Research and worldwide standards have been offered one after another, establishing the groundwork for its real-world *** paper proposes a min-sum decoding technique for enhanced Polar codes and revises the node update formula in the min-sum decoding algorithm by using the piecewise linear function to approximate the function In cosh (x) in the belief propagation decoding algorithm. Compared to the min-sum decoding algorithm, the enhanced approach improves decoding performance while somewhat increasing complexity. Compared to the belief propagation decoding algorithm, this approach decreases computational complexity significantly and is simpler to implement in hardware. Based on the min-sum method and the belief propagation algorithm, this approach is offered as a balance between complexity and performance. The simulation results demonstrate that the enhanced min-sum decoding algorithm performs similarly to its predecessor. The performance of the degree propagation decoding method is almost identical to that of the min-sum decoding technique, which is superior.
Low density parity check (LDPC) code has received more attention due to their excellent error correcting performance capabilities. An LDPC code can be decoded using iterative method like the sum-product algorithm and ...
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ISBN:
(纸本)9781479980819
Low density parity check (LDPC) code has received more attention due to their excellent error correcting performance capabilities. An LDPC code can be decoded using iterative method like the sum-product algorithm and the min-sum algorithm based on its Tanner graph. In this paper, fully parallel architecture has been designed for LDPC decoder using min-sum algorithm. This decoder modeled in Verilog synthesized and performed place and route for design using Xilinx 13.1.
Conditional termination check min-sum algorithm (MSA) using the difference of the first two minima is proposed for faster decoding speed and lower power consumption of low-density parity-check (LDPC) code decoders. Ju...
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Conditional termination check min-sum algorithm (MSA) using the difference of the first two minima is proposed for faster decoding speed and lower power consumption of low-density parity-check (LDPC) code decoders. Judging from the size of the difference in LDPC decoding scheduling, the proposed method dynamically decides whether the termination checking steps will be skipped or not. The simulation results show that the decoding speed is improved up to 7%, and the power consumption is reduced by up to 16.43% without any loss of error correcting performance. Also, the additional hardware cost of the proposed method is negligible compared to conventional LDPC decoders.
The generation of the minimum values (the first two minima and the index of the minimum) of numerous variable-to-check messages (V2CM) is the major bottleneck in efficient min-sum decoding of low-density parity-check ...
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The generation of the minimum values (the first two minima and the index of the minimum) of numerous variable-to-check messages (V2CM) is the major bottleneck in efficient min-sum decoding of low-density parity-check (LDPC) codes. This brief proposed a novel search-based compute-in-memory (CIM) based minimum values generation (MVG) scheme with two search strategies sharing two core circuits, which avoids the hardware-costly cascading of comparators and multiplexers necessary in conventional comparison-based schemes. The two shared core circuits include (1) the multi-bit content-addressable memory (MCAM) circuit for fast and concurrent search on stored operands (V2CMs) and (2) the search result evaluation (SRE) circuit to generate search result evaluation signals for the update of the minimum values. The two search strategies include (1) the sequential traversal search (STS) strategy and (2) the self-adaptive dichotomic search (SaDS) strategy for low- and high-precision decoding scenarios. Eventually, with the 14nm FinFET design kit, simulation results show that, in terms of area-delay complexity (ADC), the proposed MVG scheme achieves an average of 83% reduction in both low- and high-precision-scenarios, over the conventional comparison-based schemes.
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