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Efficient implementation of iterative multi-input-multi-output orthogonal frequency-division multiplexing receiver using minimum-mean-square error interference cancellation

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IET COMMUNICATIONS 2014年第7期8卷 990-999页

作者： Han, Bing Yang, Zengli Zheng, Yahong Rosa Missouri Univ Sci & Technol Dept Elect & Comp Engn Rolla MO 65409 USA

An efficient hardware implementation scheme is proposed for iterative multi-input-multi-output orthogonal frequency-division multiplexing receiver which includes an MMSE-IC (minimum-mean-square error interference cancellation) detector, a channel estimator, a low-density parity-check (LDPC) decoder and other supporting modules. The proposed implementation uses the QR decomposition (QRD) of the complex-valued matrices with four coordinate rotation digital computer (CORDIC) cores and a back substitution to solve the MMSE-IC equations while the existing systolic array architectures require 15-38 CORDIC cores to achieve a similar throughput. The proposed 4-CORDIC QRD architecture can be configured as a 16-matrix or a 64-matrix pipelining by using a different number of multipliers combined with one-dimensional (1D) or 2D arrays of the back substitution, respectively. The channel estimator implements a commonly-used frequency domain least squares channel estimation with the canonic-signed-digits method, thanks to the character of the Zadroff-Chu sequence used as the pilot. In the LDPC decoder, the min-sum algorithm is implemented for the quasicyclic LDPC decoding. The two schemes for the MMSE-IC detector with different throughput and resource usages have been implemented in a Field Programmable Gate Array for a complete baseband turbo receiver. Their resource usages, throughputs and latencies are compared with the classic systolic array architectures, which demonstrate that the proposed receiver architecture achieves the best tradeoff between the throughput and the resource usage.

关键词： iterative methods MIMO communication OFDM modulation least mean squares methods interference suppression channel estimation parity check codes digital arithmetic systolic arrays frequency-domain analysis field programmable gate arrays cyclic codes decoding radiofrequency interference iterative multiple-input multiple-output orthogonal frequency-division multiplexing receiver minimum mean square error interference cancellation hardware implementation scheme MMSE-IC detector low-density parity-check decoder LDPC decoder QR decomposition complex-valued matrices coordinate rotation digital computer cores CORDIC cores MMSE-IC equations 4-CORDIC QRD architecture one-dimensional arrays 2D arrays 1D arrays frequency domain least square channel estimation canonic-signed-digit method Zadroff-Chu sequence character min-sum algorithm quasicyclic LDPC decoding resource usages field programmable gate array baseband turbo receiver classic systolic array architectures receiver architecture

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On Decoding Irregular Tanner Codes With Local-Optimality Guarantees

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IEEE TRANSACTIONS ON INFORMATION THEORY 2014年第1期60卷 191-211页

作者： Halabi, Nissim Even, Guy Tel Aviv Univ Sch Elect Engn IL-69978 Tel Aviv Israel

We consider decoding of binary linear Tanner codes using message-passing iterative decoding and linear-programming (LP) decoding in memoryless binary-input output-symmetric (MBIOS) channels. We present new certificates that are based on a combinatorial characterization for the local optimality of a codeword in irregular Tanner codes with respect to any MBIOS channel. This characterization is a generalization of (Arora et al., Proc. ACM Symp. Theory of Computing, 2009) and (Vontobel, Proc. Inf. Theory and Appl. Workshop, 2010) and is based on a conical combination of normalized weighted subtrees in the computation trees of the Tanner graph. These subtrees may have any finite height (even equal or greater than half of the girth of the Tanner graph). In addition, the degrees of local-code nodes in these subtrees are not restricted to two (i.e., these subtrees are not restricted to skinny trees). We prove that local optimality in this new characterization implies maximum-likelihood (ML) optimality and LP optimality, and show that a certificate can be computed efficiently. We also present a new message-passing iterative decoding algorithm, called normalized weighted min-sum (NWMS). NWMS decoding is a belief-propagation (BP) type algorithm that applies to any irregular binary Tanner code with single parity-check local codes (e. g., low-density and high-density parity-check codes). We prove that if a locally optimal codeword with respect to height parameter exists (whereby notably is not limited by the girth of the Tanner graph), then NWMS decoding finds this codeword in iterations. The decoding guarantee of the NWMS decoding algorithm applies whenever there exists a locally optimal codeword. Because local optimality of a codeword implies that it is the unique ML codeword, the decoding guarantee also provides an ML certificate for this codeword. Finally, we apply the new local-optimality characterization to regular Tanner codes, and prove lower bounds on the noise threshol

关键词： Error bounds factor graphs graph cover IDPC codes linear programming (LP) decoding local optimality max-product algorithm maximum-likelihood (ML) certificate memoryless binary-input output-symmetric (MBIOS) channel message-passing algorithms min-sum algorithm Tanner codes thresholds

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Graphical Interface for Simulation and Analysis of LDPC Block Codes 34th

Graphical Interface for Simulation and Analysis of LDPC Bloc...

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IEEE Central America and Panama Convention (CONCAPAN XXXIV)

作者： Medina, C. Zambrano, M. Iglesias, E. Univ Tecnol Panama Panama City Panama

ISBN: (纸本)9781479975846

Low density parity check (LDPC) codes are one of the error-correction codes more versatile, promising and important, and have been adopted in most of the current communication standards. Given the actual and future relevance of these codes, we have developed a graphical interface for simulation and performance analysis considering several factors that affect their encoding and decoding. Thus, this interface could be useful in the design process of these codes, and also as a teaching-learning tool on this topic. In addition to the description of the interface and the analysis of simulations, importance of LDPC codes and graphical interfaces is discussed, the set of parameters and criteria considered in the simulations are described and some improvements to the current interface are suggested.

关键词： bit-flipping algorithm min-sum algorithm sum-prod algorithm LDPC codes LDPC codes decoding graphical interface

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Modified Tree Structure Approach for Finding the First Two minimum Values 2

Modified Tree Structure Approach for Finding the First Two M...

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2nd IEEE China summit / International Conference on Signal and Information Processing (IEEE ChinaSIP)

作者： Cui, Weiwei Yang, Yi Jiang, Xueqin Kim, Sooyoung Donghua University China

ISBN: (纸本)9781479954032

In the min-sum decoding algorithm of low-density parity-check (LDPC) codes, for a given set of input values to one check node, efficient approachs for finding the first and the second minimum values are greatly needed for the low complexity decoder. In this paper, based on the tree structure (TS) approach, we propose the modified TS (MTS) approach, which requires less number of comparisons to find the first and the second minimum values. Therefore, the hardware cost of the proposed MTS approach is lower than that of the TS approach.

关键词： Low-density parity-check (LDPC) code min-sum algorithm comparison first minimum value second minimum value

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Image registration using BP-SIFT

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JOURNAL OF VISUAL COMMUNICATION AND IMAGE REPRESENTATION 2013年第4期24卷 448-457页

作者： Zhu, Yingxuan Cheng, Samuel Stankovic, Vladimir Stankovic, Lina Syracuse Univ Dept Elect Engn & Comp Sci Syracuse NY 13244 USA Univ Oklahoma Sch Elect & Comp Engn Tulsa OK 74135 USA Univ Strathclyde Dept Elect & Elect Engn Glasgow G1 1XW Lanark Scotland

Scale Invariant Feature Transform (SIFT) is a powerful technique for image registration. Although SIFT descriptors accurately extract invariant image characteristics around keypoints, the commonly used matching approaches of registration loosely represent the geometric information among descriptors. In this paper, we propose an image registration algorithm named BP-SIFT, where we formulate keypoint matching of SIFT descriptors as a global optimization problem and provide a suboptimum solution using belief propagation (BP). Experimental results show significant improvement over conventional SIFT-based matching with reasonable computation complexity. (c) 2013 Elsevier Inc. All rights reserved.

关键词： Image registration Belief propagation SIFT RANSAC min-sum algorithm Keypoint matching Descriptors matching Image processing

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Message-Passing algorithms and Improved LP Decoding

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IEEE TRANSACTIONS ON INFORMATION THEORY 2012年第12期58卷 7260-7271页

作者： Arora, Sanjeev Daskalakis, Constantinos Steurer, David Princeton Univ Dept Comp Sci Princeton NJ 08540 USA MIT Dept Elect Engn & Comp Sci Cambridge MA 02139 USA Cornell Univ Dept Comp Sci Ithaca NY 14850 USA

Linear programming (LP) decoding for low-density parity-check codes (and related domains such as compressed sensing) has received increased attention over recent years because of its practical performance-coming close to that of iterative decoding algorithms-and its amenability to finite-blocklength analysis. Several works starting with the work of Feldman et al. showed how to analyze LP decoding using properties of expander graphs. This line of analysis works for only low error rates, about a couple of orders of magnitude lower than the empirically observed performance. It is possible to do better for the case of random noise, as shown by Daskalakis et al. and Koetter and Vontobel. Building on work of Koetter and Vontobel, we obtain a novel understanding of LP decoding, which allows us to establish a 0.05 fraction of correctable errors for rate-1/2 codes;this comes very close to the performance of iterative decoders and is significantly higher than the best previously noted correctable bit error rate for LP decoding. Our analysis exploits an explicit connection between LP decoding and message-passing algorithms and, unlike other techniques, directly works with the primal linear program. An interesting byproduct of our method is a notion of a "locally optimal" solution that we show to always be globally optimal (i.e., it is the nearest codeword). Such a solution can in fact be found in near-linear time by a "reweighted" version of the min-sum algorithm, obviating the need for LP. Our analysis implies, in particular, that this reweighted version of the min-sum decoder corrects up to a 0.05 fraction of errors.

关键词： Linear programming (LP) decoding low-density parity-check (LDPC) codes message-passing algorithms min-sum algorithm

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Intensity Reflection Coefficient Based min-sum Decoding for Low Density Parity Check Codes

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FREQUENZ 2012年第7-8期66卷 229-238页

作者： Islam, Mohammad Rakibul Mahmood, Khandaker Sultan Oshim, Md Farhan Tasnim Farazi, Md Moshiur Rahman Islamic Univ Technol Dept Elect & Elect Engn Dhaka 1704 Bangladesh

Low Density Parity Check Codes (LDPC) give groundbreaking performance which is known to approach Shannon's limits for sufficiently large block length. Historically and recently, LDPC have been known to give superior performance than concatenated coding. In the following paper, a proposal to modify the standard min-sum (MS) algorithm for decoding LDPC codes is presented. This is done by introduction of a factor, intensity reflection coefficient (IRC), kappa in the check to bit node updating process. Simulation results demonstrate that the proposed algorithms are effective in imparting a better performance in terms of a lower bit error rate (BER) at low to medium signal to noise ratio (SNR) when compared to the traditional MS or Belief Propagation (BP) algorithm while adding a minimum amount of complexity. The proposed algorithm results in a reduced hardware complexity when implemented in VLSI.

关键词： Low-density parity-check codes min-sum algorithm belief propagation algorithm IRC bit error rate (BER) computational complexity

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Resource Allocation via Message Passing

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INFORMS JOURNAL ON COMPUTING 2011年第2期23卷 205-219页

作者： Moallemi, Ciamac C. Van Roy, Benjamin Columbia Univ Grad Sch Business New York NY 10027 USA Stanford Univ Dept Management Sci & Engn Stanford CA 94305 USA

We propose a message-passing paradigm for resource allocation problems. This serves to connect ideas from the message-passing literature, which has primarily grown out of the communications, statistical physics, and artificial intelligence communities, with a problem central to operations research. This also provides a new framework for decentralized management that generalizes price-based systems by allowing incentives to vary across activities and consumption levels. We demonstrate that message-based incentives, which are characterized by a new equilibrium concept, lead to system-optimal behavior for convex resource allocation problems yet yield allocations superior to those from price-based incentives for nonconvex problems. We describe a distributed and asynchronous message-passing algorithm for computing equilibrium messages and allocations, and we demonstrate its merits in the context of a network resource allocation problem.

关键词： message-passing algorithms min-sum algorithm resource allocation convex optimization decentralized optimization

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Cost-effective variable node using thermalcode addition for LDPC decoders

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IEICE ELECTRONICS EXPRESS 2011年第23期8卷 1948-1953页

作者： Yang, Po-Hui Liu, Jia-Ping Natl Yunlin Univ Sci & Technol Dept Elect Engn Yunlin 640 Taiwan

The current paper presents thermalcode addition technology as applied to an LDPC decoder to replace a variable node unit in the traditional adder. The proposed irregular quantization of thermalcode addition can generate information with regularity, which makes addition to the variable node executable by combinational logic circuit. With the original BER performance, code rate 1/2, and matrix (1296,648) in 802.11n standard, the simulation and logic synthesis results reveal that the presented LDPC decoder can save up to 21% of the hardware area.

关键词： LDPC decoder min-sum algorithm variable node

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Analysis of Performance and Implementation Complexity of Simplified algorithms for Decoding Low-Density Parity-Check codes

Analysis of Performance and Implementation Complexity of Sim...

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Globecom Workshops

作者： Chandrasetty, Vikram Arkalgud Aziz, Syed Mahfuzul Univ S Australia Sch Elect & Informat Engn Mawson Lakes SA 5095 Australia

ISBN: (纸本)9781424488650

This paper presents a novel technique to significantly reduce the implementation complexity of Low-Density Parity-Check (LDPC) decoders. The proposed technique uses high precision soft messages at the variable nodes but scales down the extrinsic message length, which reduces the number of interconnections between variable and check nodes. It also simplifies the check node operation. The effect on performance and complexity of the decoders due to such simplification is analyzed. A prototype model of the proposed decoders compliant with the WiMax application standard has been implemented and tested on Xilinx Virtex 5 FPGA. The implementation results show that the proposed decoders can achieve significant reduction in hardware complexity with comparable decoding performance to that of min-sum algorithm based decoders. The proposed decoders are estimated to achieve an average throughput in the range of 6 - 11 Gbps, even with short code lengths.

关键词： FPGA LDPC decoder WiMax WiMax application check node operation decoding decoding field programmable gate arrays implementation complexity low density parity check codes min-sum algorithm parity check codes performance analysis simplified algorithms

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