检索结果-内蒙古大学图书馆

Globecom Workshops

作者： Chandrasetty, Vikram Arkalgud Aziz, Syed Mahfuzul Univ S Australia Sch Elect & Informat Engn Mawson Lakes SA 5095 Australia

ISBN: (纸本)9781424488650

This paper presents a novel technique to significantly reduce the implementation complexity of Low-Density Parity-Check (LDPC) decoders. The proposed technique uses high precision soft messages at the variable nodes but scales down the extrinsic message length, which reduces the number of interconnections between variable and check nodes. It also simplifies the check node operation. The effect on performance and complexity of the decoders due to such simplification is analyzed. A prototype model of the proposed decoders compliant with the WiMax application standard has been implemented and tested on Xilinx Virtex 5 FPGA. The implementation results show that the proposed decoders can achieve significant reduction in hardware complexity with comparable decoding performance to that of min-sum algorithm based decoders. The proposed decoders are estimated to achieve an average throughput in the range of 6 - 11 Gbps, even with short code lengths.

关键词： FPGA LDPC decoder WiMax WiMax application check node operation decoding decoding field programmable gate arrays implementation complexity low density parity check codes min-sum algorithm parity check codes performance analysis simplified algorithms

来源：评论

学校读者我要写书评

暂无评论

Applications of Adaptive Belief Propagation Decoding for Long Reed-Solomon Codes

Applications of Adaptive Belief Propagation Decoding for Lon...

引用

2nd International Conference on Advanced Science and Technology (AST)

作者： Zheng, Zhian Pham, Dang Hai Wada, Tomohisa Univ Ryukyus Grad Sch Engn & Sci Dept Informat Engn 1 Senbaru Nishihara Okinawa 9030213 Japan Honoi Univ Technol Fac Elect & Telecommun Hanoi Vietnam

ISBN: (纸本)9783642135767

Reed-Solomon (204,188) code has been widely used in many digital multimedia broadcasting systems. This paper focuses on the low complexity derivation of adaptive belief propagation bit-level soft decision decoding for this code. Simulation results demonstrate that proposed normalized min-sum algorithm as belief propagation (BP) process provides the same decoding performance in terms of packet-error-rate as sum-product algorithm. An outer adaptation scheme by moving adaptation process of parity check matrix out of the BP iteration loop is also introduced to reduce decoding complexity. Simulation results show that the proposed two schemes perform a good trade-off between the decoding performance and decoding complexity.

关键词： Reed-Solomon codes Adaptive belief propagation sum-Product algorithm min-sum algorithm Bit-level parity check matrix Gaussian elimination

来源：评论

学校读者我要写书评

暂无评论

Design of Irregular LDPC Codes for BIAWGN Channels with SNR Mismatch

引用

IEEE TRANSACTIONS ON COMMUNICATIONS 2009年第1期57卷 6-11页

作者： Saeedi, Hamid Banihashemi, Amir H. Carleton Univ Dept Syst & Comp Engn Broadband Commun & Wireless Syst BCWS Ctr Ottawa ON K1S 5B6 Canada

Belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes over a binary input additive white Gaussian noise (BIAWGN) channel requires the knowledge of the signal-to-noise ratio (SNR) at the receiver to achieve its ultimate performance. An erroneous estimation or the absence of a perfect knowledge of the SNR at the decoder is referred to as "SNR mismatch". SNR mismatch can significantly degrade the performance of LDPC codes decoded by the BP algorithm. In this paper, using extrinsic information transfer (EXIT) charts, we design irregular LDPC codes that perform better (have a lower SNR threshold) in the presence of mismatch compared to the conventionally designed irregular LDPC codes that are optimized for zero mismatch. Considering that min-sum (MS) algorithm is the limit of BP with infinite SNR over-estimation, the EXIT functions generated in this work can also be used for the efficient analysis and design of LDPC codes under the MS algorithm.

关键词： Irregular LDPC codes signal-to-noise ratio (SNR) mismatch channel estimation error LDPC code design EXIT charts belief propagation (BP) algorithm min-sum algorithm

来源：评论

学校读者我要写书评

暂无评论

Multi-Gb/s LDPC Code Design and Implementation

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2009年第2期17卷 262-268页

作者： Sha, Jin Wang, Zhongfeng Gao, minglun Li, Li Nanjing Univ KLAPEM Inst VLSI Design Nanjing 210093 Peoples R China Oregon State Univ Sch Elect Engn & Comp Sci Corvallis OR 97331 USA

Low-density parity-check (LDPC) code, a very promising near-optimal error correction code (ECC), is being widely considered in next generation industry standards. The VLSI implementation of high-speed LDPC decoder remains a big challenge. This paper presents the construction of a new class of implementation-oriented LDPC codes, namely shift-LDPC codes. With girth optimization, this kind of codes can perform as well as computer generated random codes. More importantly, the decoder can be efficiently implemented to obtain very high decoding speeds. In addition, more than 50% of message memory can be generally saved over conventional partially parallel decoder architectures. We demonstrate the benefits of the proposed techniques with an application-specific integrated circuit (ASIC design (in 0.18-mu m CMOS) for a 8192-bit regular LDPC code, which can achieve 5 Gb/s throughput at 15 iterations.

关键词： Error correction codes (ECC) low-density parity-check (LDPC) codes min-sum algorithm parallel processing VLSI

来源：评论

学校读者我要写书评

暂无评论

High-Throughput Layered Decoder Implementation for Quasi-Cyclic LDPC Codes

引用

IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS 2009年第6期27卷 985-994页

作者： Zhang, Kai Huang, Xinming Wang, Zhongfeng Worcester Polytech Inst Dept Elect & Comp Engn Worcester MA 01609 USA Broadcom Corp Irvine CA 92617 USA

This paper presents a high-throughput decoder design for the Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. Two new techniques are proposed, including parallel layered decoding architecture (PLDA) and critical path splitting. PLDA enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids crossbar-based large interconnect network. Critical path splitting technique is based on articulate adjustment of the starting point of each layer to maximize the time intervals between adjacent layers, such that the critical path delay can be split into pipeline stages. Furthermore, min-sum and loosely coupled algorithms are employed for area efficiency. As a case study, a rate-1/2 2304-bit irregular LDPC decoder is implemented using ASIC design in 90nm CMOS process. The decoder can achieve the maximum decoding throughput of 2.2Gbps at 10 iterations. The operating frequency is 950MHz after synthesis and the chip area is 2.9mm(2).

关键词： Low-density parity-check codes quasi-cyclic codes parallel architecture layered decoding critical path splitting min-sum algorithm loosely coupled algorithm VLSI

来源：评论

学校读者我要写书评

暂无评论

High-Throughput QC-LDPC Decoders

引用

IEEE TRANSACTIONS ON BROADCASTING 2009年第2期55卷 251-259页

作者： Jiang, Nan Peng, Kewu Song, Jian Pan, Chanyong Yang, Zhixing Tsinghua Univ Dept Elect Engn Tsinghua Natl Lab Informat Sci & Technol Beijing 100084 Peoples R China

High-throughput design approaches for quasi-cyclic (QC) low-density parity-check (LDPC) decoders are presented in this paper. Three novel schemes for the horizontal process in min-sum algorithm and its revisions are derived to reduce design and implementation complexity. The schemes can be directly applied for variant QC codes and easily pipelined to increase the operating frequency of the decoder. Some improvements of the semi-parallel architecture are proposed to enhance throughput performance and hardware efficiency. Employing the proposed approaches, QC-LDPC decoders for Chinese Digital Television Terrestrial Broadcasting (DTTB) standard are implemented using field programmable gate array (FPGA). As shown in the results, the proposed approaches can substantially improve the throughput performance, as well as the through put-and-hardware tradeoff, of decoders with semi-parallel architecture.

关键词： LDPC LDPC decoder min-sum algorithm pipeline QC-LDPC soft-decision decoder throughput

来源：评论

学校读者我要写书评

暂无评论

Message-Passing algorithms and Improved LP Decoding

Message-Passing Algorithms and Improved LP Decoding

引用

41st Annual ACM Symposium on Theory of Computing

作者： Arora, Sanjeev Daskalakis, Constantinos Steurer, David Princeton Univ Princeton NJ 08544 USA

ISBN: (纸本)9781605586137

Linear programming decoding for low-density parity check codes (and related domains such as compressed sensing) has received increased attention over recent years because of its practical performance -coming close to that of iterative decoding algorithms- and its amenability of finite-blocklength analysis. Several works starting with the work of Feldman et al. showed how to analyze LP decoding using properties of expander graphs. This line of analysis works for only low error rates, about a couple of orders of magnitude lower than the empirically observed performance. It is possible to do better for the case of random noise, as shown by Daskalakis et al. and Koetter and Vontobel. Building on work of Koetter and Vontobel, we obtain a novel understanding of LP decoding, which allows us to establish a 0.05-fraction of correctable errors for rate-1/2 codes;this comes very close to the performance of iterative decoders and is significantly higher than the best previously noted correctable bit error rate for LP decoding. unlike other techniques, our analysis directly works with the primal linear program and exploits and explicit connection between LP decoding and message passing algorithms. An interesting byproduct of our method is a notion of a "locally optimal" solution that we show to always be globally optimal (i.e., it is the nearest codeword). Such a solution can in fact be found in near-linear time by a "re-weighted" version of the min-sum algorithm, obviating the need for linear programming. Our analysis implies, in particular, that this re-weighted version of the min-sum decoder corrects up to a 0.05-fraction of errors.

关键词： LDPC codes LP decoding min-sum algorithm message-passing algorithms

来源：评论

学校读者我要写书评

暂无评论

On implementation of min-sum algorithm and its modifications for decoding low-density parity-check (LDPC) codes

引用

IEEE TRANSACTIONS ON COMMUNICATIONS 2005年第4期53卷 549-554页

作者： Zhao, JG Zarkeshvari, F Banihashemi, AH Carleton Univ BCWS Ottawa ON K1S 5B6 Canada Carleton Univ Dept Syst & Comp Engn Ottawa ON K1S 5B6 Canada

The effects of clipping and quantization on the performance of the min-sum algorithm for the decoding of low-density parity-check (LDPC) codes at short and intermediate block lengths are studied. It is shown that in many cases, only four quantization bits suffice to obtain close to ideal performance over a wide range of signal-to-noise ratios. Moreover, we propose modifications to the min-sum algorithm that improve the performance by a few tenths of a decibel with just a small increase in decoding complexity. A quantized version of these modified algorithms is also studied. It is shown that, when optimized, modified quantized min-sum algorithms perform very close to, and in some cases even slightly outperform, the ideal belief-propagation algorithm at observed error rates.

关键词： clipping iterative decoding algorithms low-density parity-check (LDPC) codes max-product algorithm max-sum algorithm min-sum algorithm modified min-sum algorithms quantization

来源：评论

学校读者我要写书评

暂无评论

Max-product for maximum weight matching: Convergence, correctness, and LP duality

引用

IEEE TRANSACTIONS ON INFORMATION THEORY 2008年第3期54卷 1241-1251页

作者： Bayati, Mobsen Shah, Devavrat Sharma, Mayank Microsoft Res Redmond WA 98052 USA MIT Dept Elect Engn & Comp Sci Cambridge MA 02139 USA IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

Max-product "belief propagation" (BP) is an iterative, message-passing algorithm for finding the maximum a posteriori (MAP) assignment of a discrete probability distribution specified by a graphical model. Despite the spectacular success of the algorithm in many application areas such as iterative decoding and combinatorial optimization, which involve graphs with many cycles, theoretical results about both the correctness and convergence of the algorithm are known in only a few cases (see Section I for references). In this paper, we will prove the correctness and convergence of max-product for finding the maximum weight matching (MWM) in bipartite graphs. Even though the underlying graph of the MWM problem has many cycles, somewhat surprisingly we show that the max-product algorithm converges to the correct MWM as long as the MWM is unique. We provide a bound on the number of iterations required and show that for a graph of size n, the computational cost of the algorithm scales as O(n(3)), which is the same as the computational cost of the best known algorithms for finding the MWM. We also provide an interesting relation between the dynamics of the max-product algorithm and the auction algorithm, which is a well-known distributed algorithm for solving the MWM problem.

关键词： auction algorithm belief propagation (BP) distributed optimization linear programming Markov random fields maximum weight matching (MWM) max-product algorithm message-passing algorithms min-sum algorithm

来源：评论

学校读者我要写书评

暂无评论

Area-efficient min-sum decoder design for high-rate quasi-cyclic low-density parity-check codes in magnetic recording

引用

IEEE TRANSACTIONS ON MAGNETICS 2007年第12期43卷 4117-4122页

作者： Zhong, Hao Xu, Wei Xie, Ningde Zhang, Tong Rensselaer Polytech Inst Troy NY 12180 USA LSI Corp San Jose CA 95134 USA

We report a silicon area efficient method for designing a quasi-cyclic (QC) low-density parity-check (LDPC) code decoder. Our design method is geared to magnetic recording that demands high code rate and very high decoding throughput under stringent silicon cost constraints. The key to designing the decoder is to transform the conventional formulation of the min-sum decoding algorithm in such a way that we can readily develop a hardware architecture with several desirable features: 1) silicon area saving potential inherent in the min-sum algorithm for high-rate codes can be fully exploited;2) the decoder circuit critical path may be greatly reduced;and 3) check node processing and variable node processing can operate concurrently. For the purpose of demonstration, we designed application-specific integrated circuit decoders for four rate-8/9 regular-(4, 36) QC-LDPC codes that contain 512-byte, 1024-byte, 2048-byte, and 4096-byte user data per codeword, respectively. Synthesis results show that our design method can meet the beyond-2 Gb/s throughput requirement in future magnetic recording at minimal silicon area cost.

关键词： decoder low-density parity-check (LDPC) min-sum algorithm very large scale integration (VLSI)

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：