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A neural network accelerated optimization method for FPGA

JOURNAL OF COMBINATORIAL OPTIMIZATION 2024年第5期47卷 84-84页

作者： Hu, Zhengwei Zhu, Sijie Wang, Leilei Cao, Wangbin Xie, Zhiyuan North China Elect Power Univ Dept Elect & Commun Engn Baoding 071003 Peoples R China

A neural network accelerated optimization method for FPGA hardware platform is proposed. The method realizes the optimized deployment of neural network algorithms for FPGA hardware platforms from three aspects: computational speed, flexible transplantation, and development methods. Replacing multiplication based on mitchell algorithm not only breaks through the speed bottleneck of neural network hardware acceleration caused by long multiplication period, but also makes the parallel acceleration of neural network algorithm get rid of the dependence on the number of hardware multipliers in FPGA, which can give full play to the advantages of FPGA parallel acceleration and maximize the computing speed. Based on the configurable strategy of neural network parameters, the number of network layers and nodes within layers can be adjusted according to different logical resource of FPGA, improving the flexibility of neural network transplantation. The adoption of HLS development method overcomes the shortcomings of RTL method in designing complex neural network algorithms, such as high difficulty in development and long development cycle. Using the Cyclone V SE 5CSEBA6U23I7 FPGA as the target device, a parameter configurable BP neural network was designed based on the proposed method. The usage of logical resources such as ALUT, Flip-Flop, RAM, and DSP were 39.6%, 40%, 56.9%, and 18.3% of the pre-optimized ones, respectively. The feasibility of the proposed method was verified using MNIST digital recognition and facial recognition as application scenarios. Compare to pre-optimization, the test time of MNIST number recognition is reduced to 67.58%, and the success rate was lost 0.195%. The test time for facial recognition applications was reduced to 69.571%, and the success rate of combining LDA algorithm was lost within 4%.

关键词： Field programmable gate array Neural network Hardware acceleration mitchell algorithm High-level synthesis

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A Review of Logarithmic Multiplier Hardware Architectures

A Review of Logarithmic Multiplier Hardware Architectures

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International Conference on Decision Aid Sciences and Applications (DASA)

作者： Kantipudi, M. V. V. Prasad Sailaja, Vemuri Sanipini, Venkata Kiran Symbiosis Int Deemed Univ Symbiosis Inst Technol Pune 412115 Maharashtra India Pragati Engn Coll Elect & Commun Engn Surampalem India Aditya Coll Engn & Technol Elect & Commun Engn Surampalem India

ISBN: (纸本)9781665495011

Multiplication is basics for any arithmetic operations of central processing unit and graphical processing units. Nowadays multipliers are widely used in digital image processing, digital signal processing, network security, and multimedia applications. Therefore, high performance multipliers are mandatory to design and implement fast multimedia devices. Several high-performance multipliers are suggested in the last few decades by researchers such as booth multiplication, wallace tree multiplication, bough wooley multipliers, karatsuba multipliers and logarithmic multipliers. Among the various schemes of multiplication algorithms, logarithmic multiplication is widely used in image processing and multimedia applications due its high performance. This paper analyses the very large-scale integration (VLSI) characteristics of different logarithmic multipliers in terms of speed, power consumption and area utilization. Based on the detailed review, this paper suggests that logarithmic multiplier which uses an approximation-based multiplier by using the concept of double-sided fault distribution is deemed as high-accuracy baseline design for implementing instead of using the mitchell-based algorithm. This approximation-based design is also suitable for area utilization and power consumption.

关键词： Approximate Multiplier mitchell algorithm Convolutional Networks Multiply Accumulate Logarithmic Number System

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An Improved Logarithmic Multiplier for Media Processing

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2019年第6期91卷 561-574页

作者： Ahmed, Syed Ershad Srinivas, M. B. BITS Pilani Elect Dept Hyderabad Campus Hyderabad India BML Munjal Univ Sch Engn & Technol Gurgaon India

As the modern computing systems become increasingly embedded and portable, a growing set of applications in media processing (graphics, audio, video, and image) has evolved. Multiplication is the operation that is most often used in these applications which when accomplished in logarithmic number system results in an area efficient and faster design. In this work, the authors describe a technique that combines mitchell's approximation with a novel hardware truncation scheme resulting in an iterative multiplier with improved precision and reduced area. Further, a new fractional predictor combined with an existing truncated logarithmic shifter significantly reduces the overall hardware cost of the multiplier. Simulations carried out on benchmark image processing applications such as Lena, cameraman and pirate clearly indicate that the proposed technique performs better than those available in the literature.

关键词： mitchell algorithm Logarithmic number system Multiplication Image processing

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Design and Implementation of Logarithmic Multiplier Using FinFETs for Low Power Applications 3rd

Design and Implementation of Logarithmic Multiplier Using Fi...

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3rd International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT)

作者： Kumbargeri, Vaishnavi Mahale, Anusha Aradhya, H. V. Ravish RV Coll Engn Dept ECE Bangalore Karnataka India

ISBN: (纸本)9789811358029;9789811358012

In all processing systems, multiplication is one of the computation-intensive operations demanding more resources. Hence, multiplication operations demand more time, power and resources. One of the better solutions is mitchell's algorithm. mitchell-based logarithmic multiplier is used as alternative approach which improves the speed, at the cost of accuracy. This paper presents the logarithmic multiplier implementation using the FinFETs. The hardware level simulation is done in Cadence Virtuoso using 18 nm technology. Comparison of power consumption of logarithmic multiplier using MOSFETs and FinFETs is presented. A 93.69% power reduction is seen in the proposed design as compared with the previous work.

关键词： Logarithmic multiplier FinFET mitchell algorithm

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An Area and Delay Efficient Logarithmic Multiplier

An Area and Delay Efficient Logarithmic Multiplier

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Contemporary Computing and Applications (IC3A), International Conference on

作者： Navteja Alla Syed Ershad Ahmed Department of Electrical Engineering BITS Pilani Hyderabad India

ISBN: (数字)9781728154329

ISBN: (纸本)9781728154336

Multiplication is an ubiquitous operation in growing set of media processing applications (graphics, audio, video, and image). Many of these applications, however, possess an inherent quality of error resilience. Thus the multipliers, that are not very precise but return an approximate value, can be utilized in such applications. Such units, it may be anticipated, may result in area savings while also resulting in reduced power consumption. In recent years, logarithmic number system (LNS) has been increasingly used as an alternative to the binary number system as it converts multiplication to addition resulting in simplified hardware. However, they suffer from inherent error and any efforts in improving their accuracy would help find their increased usage in arithmetic computations with efficient hardware. In this paper, a method that combines mitchell's approximation with a hardware pruning technique that leads to an area efficient multiplier architecture without compromise on precision. Simulations carried out prove that the proposed multiplier architectures are efficient both in area and delay when compared to existing designs.

关键词： Logarithmic Number System mitchell algorithm Logarithmic Multiplier Logarithmic Shifter counting system Multiplying circuits Multiplication audio video inherent error error-resilience Logarithmic Computer hardware Power consumption

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An Iterative Logarithmic Multiplier with Improved Precision 23

An Iterative Logarithmic Multiplier with Improved Precision

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23rd IEEE Symposium on Computer Arithmetic (ARITH)

作者： Ahmed, Syed Ershad Kadam, Sanket Srinivas, M. B. BITS Pilani Dept Elect & Elect Engn Hyderabad Campus Hyderabad Andhra Pradesh India

ISBN: (纸本)9781509016150

Recent studies have demonstrated the potential for achieving higher area and power saving with approximate computation in error tolerant applications involving signal and image processing. Multiplication is a major mathematical operation in these applications which when performed in logarithmic number system results in faster and energy efficient design. In this paper, the authors present a method which combines the mitchell's approximation and hardware truncation scheme in a novel way resulting in an iterative multiplier with improved precision and area. Further, proposed truncation approach and fractional predictor significantly reduce the overall hardware requirement of the multiplier. Experimental results prove the superiority of the proposed multiplier over previous designs.

关键词： Logarithmic Number System mitchell algorithm Iterative Multiplier Logarithmic Shifter

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High Accuracy Binary Logarithmic Conversion using Range Mapping for DSP Applications

High Accuracy Binary Logarithmic Conversion using Range Mapp...

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IEEE Asia Pacific Conference on Circuit and System (APCCAS)

作者： Low, Joshua Yung Lih Jong, Ching Chuen Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore

ISBN: (纸本)9781424474561

This paper presents a high accuracy mitchell-based logarithmic conversion algorithm suitable for integrated circuit implementation. A novel technique named range mapping is proposed to compress the range of approximation to one-quarter of that of the mitchell's fraction, m. A 3-region piecewise linear approximation is then applied on the compressed range. Simulation results show that the proposed algorithm achieves both low absolute error and percentage error of 0.0037999 and 0.064002% respectively.

关键词： Binary logarithm mitchell algorithm Range mapping Logarithmic number system (LNS) ASIC for DSP

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High Accuracy Binary Logarithmic Conversion using Range Mapping for DSP Applications

High Accuracy Binary Logarithmic Conversion using Range Mapp...

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IEEE Asia Pacific Conference on Circuits and Systems

作者： Joshua Yung Lih Low Ching Chuen Jong School of Electrical and Electronic Engineering Nanyang Technological University

ISBN: (纸本)9781424474547

关键词： Binary logarithm mitchell algorithm Range mapping Logarithmic number system (LNS) ASIC for DSP

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