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IEEE/ACM International Workshop on Behavioral modeling and Simulation (BMAS 2000)

作者： Huang, XL Mantooth, HA Univ Arkansas Dept Elect Engn Fayetteville AR 72701 USA

ISBN: (纸本)0769508936

This paper describes a novel modeling methodology for electrothermal effects in large mixed-signal circuits. It is accomplished by developing analog event-driven electrothermal and thermal models in an analog hardware description language (AHDL). The large-scale mixed-signal circuits represented by the analog event-driven models can be analyzed more efficiently than using standard analog models.

关键词： electrothermal analog event-driven modeling thermal modeling mixed-signal modeling

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Event-Driven Electrothermal modeling of mixed-signal Circuits 00

Event-Driven Electrothermal Modeling of Mixed-Signal Circuit...

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Proceedings of the 2000 IEEE/ACM international workshop on Behavioral modeling and simulation

作者： Xiaoling Huang H. Alan Mantooth

ISBN: (纸本)9780769508931

关键词： Thermal modeling Analog Event-Driven modeling Electrothermal mixed-signal modeling

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Analog behavior modeling and processing using AnaVHDL

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ANALOG INTEGRATED CIRCUITS AND signal PROCESSING 1998年第2期16卷 173-183页

作者： Ye, L Carter, HW Univ Cincinnati ECECS Dept Cincinnati OH 45221 USA

This article describes briefly the AnaVHDL language, which introduces minimal extensions to VHDL93 to construct a useful and robust language to model mixed-signal systems at multiple levels of abstraction from different equation level to abstract system level and across multiple technologies employing both discrete-event and continuous time behavior. The classification of equations to describe continuous domain system behavior is then presented. Based on the classification, a Compacted Nodal Analysis (CNA) method is used to construct the Differential/Algebraic Equation (DAE) set fur a system design.

关键词： mixed-signal modeling hardware description language compacted nodal analysis modified nodal analysis

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VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2005年第2期24卷 204-225页

作者： Pêcheux, F Lallement, C Vachoux, A Univ Paris 06 LIP6 Integrated Syst Architecture Dept F-75252 Paris France ENSPS Lab PHASE ERM F-67412 Illkirch Graffenstaden France Ecole Polytech Fed Lausanne LSM Microelect Syst Lab CH-1015 Lausanne Switzerland

This paper focuses on commonalities and differences between the two mixed-signal hardware description languages, VHDL-AMS and Verilog-AMS, in the case of modeling heterogeneous or multidiscipline systems. The paper has two objectives. The first one is modeling the structure and the behavior of an airbag system using both the VHDL-AMS and the Verilog-AMS languages. Such a system encompasses several time abstractions (i.e., discrete-time and continuous-time), several disciplines, or energy domains (i.e., electrical, thermal, optical, mechanical, and chemical), and several continuous-time description formalisms (i.e., conservative-law and signal-flow descriptions). The second objective is to discuss the results of the proposed modeling process in terms of the descriptive capabilities of the VHDL-AMS and Verilog-AMS languages and of the generated simulation results. The tools used are the Advance-MS from Mentor Graphics for VHDL-AMS and the AMS Simulator from Cadence Design Systems for Verilog-AMS. This paper shows that both languages offer effective means to describe and simulate multidiscipline systems, though using different descriptive approaches. It also highlights current tool limitations, since full language definitions are not yet supported.

关键词： accelerometer chemical system EKV MOS model generalized Kirchhoff laws mixed-signal modeling multidiscipline modeling optical link airbag thermoelectrical interactions Verilog-AMS VHDL-AMS

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Design of a Digital PLL Real Number Model Using SystemVerilog 8

Design of a Digital PLL Real Number Model Using SystemVerilo...

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8th International Conference on Modern Circuit and System Technologies (MOCAST)

作者： Georgoulopoulos, Nikolaos Hatzopoulos, Alkiviadis Aristotle Univ Thessaloniki Dept Elect & Comp Engn Thessaloniki Greece

ISBN: (纸本)9781728111841

mixed-signal applications constitute a significant trend in the semiconductor industry. Huge effort is focused on creating fast and accurate mixed-signal designs, which include both analog and digital parts. A widely used mixed-signal circuit in modern electronics is the phase-locked loop (PLL). Phase-locked loop is mainly exploited as a frequency synthesizer, for the generation of a frequency which is a multiple of an input frequency. Apart from that, a PLL can be applied for signal demodulation, signal recovery from noise, or clock distribution in various digital logic circuits. In this work, a digital phase-locked loop real number model using SystemVerilog is presented, in order to greatly improve simulation efficiency while keeping accuracy in a satisfying level. The proposed digital PLL real number model consists of a phase frequency detector (PFD), a charge pump, a loop filter, a voltage-controlled oscillator (VCO) and a frequency divider. The target output frequency of 1.2GHz is succeeded for the system clock, using a reference clock of 200MHz. The design and simulation of the proposed PLL model was accomplished using the Cadence Incisive Enterprise Simulator. Moreover, the proposed model is compared to a Verilog-A charge-pump PLL, having its design implemented and simulated in Cadence Virtuoso and Spectre. In all test cases, the presented SystemVerilog-based real number model displays high simulation time gains, along with satisfying accuracy.

关键词： Real number modeling mixed-signal modeling SystemVerilog Phase-locked loop Voltage-controlled oscillator Low-pass filter

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Efficiency Evaluation of a SystemVerilog-based Real Number Model 7

Efficiency Evaluation of a SystemVerilog-based Real Number M...

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7th International Conference on Modern Circuits and Systems Technologies (MOCAST)

作者： Georgoulopoulos, Nikolaos Hatzopoulos, Alkiviadis Aristotle Univ Thessaloniki Dept Elect & Comp Engn Thessaloniki Greece

ISBN: (纸本)9781538647882

Real Number modeling (RNM) is the process of modeling an analog circuit's behavior as signal flow model. This means that every output of an analog component is sampled, in a discrete manner, from the inputs and the internal state. The model detects an event and decides the time to carry out a computation. A SystemVerilog behavioral real number model for a comparator is presented, in order to improve simulation efficiency. The comparator model simulation time completes in only 154ms, which can be utilized effectively in high-speed analog-to-digital converters (ADCs). The proposed model is compared to three different models: a transistor-level CMOS comparator, a Verilog-A and a Verilog-AMS with wreal models. 65nm CMOS technology library was used for the comparator designs in Cadence Virtuoso. The simulation runs took place in Spectre (for transistor-level SPICE model) and AMS Simulator (for SystemVerilog, Verilog-A and Verilog-AMS with wreal). In all cases, the presented SystemVerilog model displays high gains in simulation run time, along with satisfying accuracy.

关键词： Real number modeling mixed-signal modeling System Verilog Comparator Analog modeling

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Real Number modeling of a Flash ADC Using SystemVerilog 4

Real Number Modeling of a Flash ADC Using SystemVerilog

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4th Panhellenic Conference on Electronics and Telecommunications (PACET)

作者： Georgoulopoulos, Nikolaos Hatzopoulos, Alkiviadis Aristotle Univ Thessaloniki Dept Elect & Comp Engn Thessaloniki Greece

ISBN: (纸本)9781538622889;9781538622872

Real Number modeling (RNM) is the process of modeling an analog circuit's behavior as signal flow model. This means that every output of an analog component is sampled, in a discrete manner, from the inputs and the internal state. The model detects an event and decides the time to carry out a computation. A SystemVerilog behavioral real number model for a 3-bit flash analog-to-digital converter (ADC) is presented, in order to improve simulation efficiency. The ADC model simulation time completes in only 1.23s, which can be utilized effectively in high-frequency applications. The proposed model is compared to three different models: a transistor-level flash ADC, a Verilog-A ADC model and a Verilog-AMS with wreal ADC model. 65nm CMOS technology library was used for the flash ADC designs in Cadence Virtuoso. The simulation runs took place in Spectre (for transistor-level SPICE model) and AMS Simulator (for SystemVerilog, Verilog-A and Verilog-AMS with wreal). In all cases, the presented SystemVerilog model displays reduced simulation run time, in comparison with the other models, along with satisfying accuracy.

关键词： Real number modeling mixed-signal modeling SystemVerilog Comparator Analog-to-digital converter Analog modeling

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Using reduced-order models in D/A converter testing

Using reduced-order models in D/A converter testing

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19th IEEE Instrumentation and Measurement Technology Conference (IMTC/2002)

作者： Vargha, B Schoukens, J Rolain, Y Budapest Univ Technol & Econ Dept Measurement & Informat Syst H-1117 Budapest Hungary

ISBN: (纸本)0780372182

Static models of D/A converters can efficiently be used for testing purposes. For high-resolution converters nonparametric nonlinearity tests are not practically feasible for production testing due to the long test time. modeling the device error response using a limited number of model parameters, the minimal number of required test points is significantly decreased. As a consequence, it becomes possible to estimate the error characteristics of the device from a few test points. In the paper, methods to select model parameters are discussed. The results are verified by the processed measurement data of 100 D/A converters.

关键词： digital-to-analog conversion mixed-signal modeling nonlinearity diagrams testing data converters

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A Precise and High Speed Charge-Pump PLL Model Based on SystemC/SystemC-AMS

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INTERNATIONAL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS 2012年第3期58卷 225-232页

作者： Ma, Kezheng van Leuken, Rene Vidojkovic, Maja Romme, Jac Rampu, Simonetta Pflug, Hans Huang, Li Dolmans, Guido Delft Univ Technol NL-2628 CD Delft Netherlands Holst Ctr HTC 31 NL-5656 AE Eindhoven Netherlands

The Phase Locked Loop (PLL) has become an important part of electrical systems. When designing a PLL, an efficient and reliable simulation platform for system evaluation is needed. However, the closed loop simulation of a PLL is time consuming. To address this problem, in this paper, a new PLL model containing both digital and analog parts based on SystemC/SystemC-AMS (BETA version) is presented. Many imperfections such as Voltage Control Oscillator (VCO) noise or reference jitter are included in this model. By comparing with the Matlab model, the SystemC/SystemC-AMS model can dramatically reduce simulation time. Also, by comparing with Analog Devices ADI SimPLL simulation results, Cadence simulation results and real measurement results, the accuracy of the SystemC/SystemC-AMS model is demonstrated. The paper shows the feasibility of a unified design environment for mixed-signal modelling based on SystemC/SystemC-AMS in order to reduce the cost and design time of electrical systems.

关键词： SystemC/SystemC-AMS Phase Locked Loop (PLL) radio frequency mixed-signal modeling hardware description language

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