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Correct-by-construction model-based design of reactive streaming software for multi-core embedded systems (vol 13, pg 312, 2020)

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INTERNATIONAL JOURNAL ON SOFTWARE TOOLS FOR TECHNOLOGY TRANSFER 2020年第1期22卷 33-34页

作者： Gioulekas, Fotios Poplavko, Peter Katsaros, Panagiotis Bensalem, Saddek Palomo, Pedro Aristotle Univ Thessaloniki Dept Informat Thessaloniki Greece Mentor Montbonnot St Martin France UGA VERIMAG Grenoble France Deimos Space Madrid Spain

We present a model-based design approach toward correct-by-construction implementations of reactive streaming software for multi-core systems. A system’s implementation is derived from a high-level process network model by applying semantics-preserving model transformations. The so-called fixed priority process networks (FPPNs) are programmed independently from the execution platform and combine streaming and reactive control behavior with task parallelism for utilizing multi-core processing. We first define the FPPN sequential execution semantics that specifies precedence constraints between job executions of different tasks. Applications are thus rendered such that for any given test stimuli, a deterministic output response is expected. Furthermore, we define the FPPN real-time semantics based on a timed-automata modeling framework. This is provably a functionally equivalent semantics specifying the real-time execution of FPPNs and enabling runtime managers for scheduling jobs on multi-cores. A model transformation framework has been developed for deriving executable implementations of FPPNs on the BIP (Behavior-Interaction-Priority) runtime environment, ported on multi-core platforms. Schedulability is established by static analysis of the FPPN, and it is guaranteed by construction. Thus, the developers do not need to program low-level real-time OS services (e.g., for task management) and applications are amenable to testing, as opposed to if their outputs would depend on timing behavior. We have successfully ported a guidance-navigation and control application of a satellite system, onto a radiation hardened multi-core platform. Various implementation scenarios for efficiently utilizing HW resources are illustrated, and the test results are discussed.

关键词： Process network model of computation model transformation Timed-automata Critical systems Multi-core processors

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Heterogeneous composition of models of computation

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2009年第5期25卷 552-560页

作者： Goderis, Antoon Brooks, Christopher Altintas, Ilkay Lee, Edward A. Goble, Carole Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England Univ Calif Berkeley Dept EECS Berkeley CA USA Univ Calif San Diego San Diego Supercomp Ctr San Diego CA USA

A model of computation (MoC) is a formal abstraction of execution in a computer. There is a need for composing diverse MoCs in e-science. Kepler, which is based on Ptolemy II, is a scientific workflow environment that allows for MoC composition. This paperexplains how MoCs are combined in Kepler and Ptolemy II and analyzes which combinations of MoCs are currently possible and useful. It demonstrates the approach by combining MoCs involving dataflow and finite state machines. The resulting classification should be relevant to other workflow environments wishing to combine multiple MoCs (available at http://***/heterogeneousMoCs). (C) 2009 Published by Elsevier B.V.

关键词： model of computation Scientific workflow Kepler Ptolemy II

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Heterogeneity of abstractions in EDA tools: Reviewing models of computation for many-core systems targeting intensive signal processing applications

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MICROPROCESSORS AND MICROSYSTEMS 2018年第Jun.期59卷 1-14页

作者： Ammar, Manel Abid, Mohamed Natl Engn Sch Sfax CES Lab Sfax Tunisia

Designing many-core systems for intensive signal processing applications necessitates refreshing common practices in the design of Electronic Design Automation (EDA) tools. This should change the focus of the EDA community from old-fashioned foundations including heavy implementations and time-consuming simulations, to recent engineering practices promoting rapid design and acceptable accuracy. Hence, the challenge of the EDA community comes to define a design process for many-core systems which enables four goals: modeling conciseness, estimation accuracy, design rapidity, and exploration flexibility. In this scenario, the modeling task can be defined as a delicate design phase that requires choosing the adequate model of computation (MoC) at each step of the design process. Design models at each level of abstraction provide the basis for applying analysis, synthesis or verification techniques. Since modeling concepts and techniques can have a large influence on the quality, accuracy and rapidity of results, models and corresponding abstraction levels should be well-defined with clear and unambiguous semantics. In this paper, we aim to provide an analysis and comparative overview of common MoCs used in the specification and performance analysis of intensive signal processing applications and many-core architectures. After identifying conventional classifications, we propose a new taxonomy of MoCs based on their purpose in the design flow. The heterogeneity of MoCs in EDA tools is also discussed and various tools are reviewed and compared.

关键词： model of computation Many-core Signal processing Electronic design automation model of performance model of specification

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SML-Sys: a functional framework with multiple models of computation for modeling heterogeneous system

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DESIGN AUTOMATION FOR EMBEDDED SYSTEMS 2008年第1-2期12卷 1-30页

作者： Mathaikutty, Deepak A. Patel, Hiren D. Shukla, Sandeep K. Jantsch, Axel Intel Corp Microprocessor Technol Lab Microarchitecture Res Lab Santa Clara CA 95051 USA Virginia Polytech Inst & State Univ CESCA Blacksburg VA 24061 USA Royal Inst Technol Dept Microelect & Informat Technol Stockholm Sweden

System-on-Chip and other complex distributed hardware/software systems contain heterogeneous components. High-level modeling of such systems require frameworks that provide designers with the ability to express concepts of models of computation (MoC)s as modeling constructs. Many system-level modeling frameworks and corresponding modeling notations such as Ptolemy II and SystemC-H facilitate multi-MoC modeling but are based on imperative programming languages (C++, Java, etc). In such frameworks, the computation and communication aspects between the components of models get intertwined thereby hindering its amenability to formal analysis. In this work, we illustrate function-based semantic definitions of MoCs, which are formulated in a functional framework called SML-Sys. We illustrate through a number of examples how to create system models using this functional programming paradigm.

关键词： functional programming model of computation heterogeneity modeling fidelity modeling expressiveness

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Best-order streaming model

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THEORETICAL COMPUTER SCIENCE 2011年第23期412卷 2544-2555页

作者： Das Sarma, Atish Lipton, Richard J. Nanongkai, Danupon Georgia Inst Technol Atlanta GA 30332 USA

We study a new model of computation, called best-order stream, for graph problems. Roughly, it is a proof system where a space-limited verifier has to verify a proof sequentially (i.e., it reads the proof as a stream). Moreover, the proof itself is just a specific ordering of the input data. This model is closely related to many models of computation in other areas such as data streams, communication complexity, and proof checking, and could be used in applications such as cloud computing. In this paper we focus on graph problems where the input is a sequence of edges. We show that even under this model, checking some basic graph properties deterministically requires linear space in the number of nodes. We also show that, in contrast with this, randomized verifiers are powerful enough to check many graph properties in polylogarithmic space. (C) 2010 Elsevier B.V. All rights reserved.

关键词： Data stream model of computation Communication complexity

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FunState -: An internal design representation for codesign

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2001年第4期9卷 524-544页

作者： Strehl, K Thiele, L Gries, M Ziegenbein, D Ernst, R Teich, J ETAS GmbH Res & Dev D-70469 Stuttgart Germany Swiss Fed Inst Technol Swiss Fed Inst Technol Comp Engn & Networks Lab TIK CH-8092 Zurich Switzerland Tech Univ Carolo Wilhelmina Braunschweig IDA Inst Comp & Commun Network Engn D-38106 Braunschweig Germany Univ Gesamthsch Paderborn DATE Comp Engn Lab D-33098 Paderborn Germany

In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components and scheduling mechanisms using a mixture of functional programming and state machines, It is shown how properties relevant for scheduling and verification of specification models such as Boolean dataflow, cyclostatic dataflow, synchronous dataflow, marked graphs, and communicating state machines as well as Petri nets can be represented in the FunState model of computation, Examples of methods suited for FunState are described, such as scheduling and verification. They are based on the representation of the model's state transitions in the form of a periodic graph, The feasibility of the novel approach is shown with an asynchronous transfer mode switch example.

关键词： formal verification high-level synthesis internal specification model model of computation symbolic scheduling

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Composable Finite State Machine-based modeling for Quality-of-Information-aware Cyber-physical Systems

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ACM TRANSACTIONS ON CYBER-PHYSICAL SYSTEMS 2021年第2期5卷 1–27页

作者： Rosales, Rafael Paulitsch, Michael Intel Deutschland GmbH Lilienthalstr 15 D-85579 Neubiberg Germany

Time plays a major role in the specification of Cyber-physkal Systems (CPS) behavior with concurrency, timeliness, asynchrony, and resource limits as their main characteristics. In addition to timeliness, the specification of CPS needs to assess and unambiguously define its behavior with respect to the other Quality-of-Information (QoI) properties: (1) Correctness, (2) Completeness, (3) Consistency, and (4) Accuracy. Very often, CPS need to handle these QoI properties, and any combination thereof, multiple times when performing computation and communication processes. However, a model-driven and systematic approach to specify CPS behavior that jointly considers combined QoI aspects is possible but missing in existing methodologies. As the first contribution of this work, we provide an extension to an established model of computation (MoC) based on "Functions driven by Finite State Machine" (FunState) to enable a model-driven composition mechanism to create CPS behavior specifications from reusable components. Second, we present a novel set of design patterns to illustrate the modeling of QoI-aware CPS specifications that can be applied in several state-of-the-art Electronic System Level (ESL) methodologies. The time semantics of the MoC are formalized using the tagged-signal-model, and the presented model-driven approach enables the composition of multiple design patterns. The main benefits of the presented model-driven approach and design patterns to create CPS specifications are as follows: (a) reduce modeling effort, errors, and time through the reuse of known recipes to reincurring tasks and allow to automatically generate repetitive control flows based on extended Finite State Machines;(b) increase system robustness and facilitate the creation of holistic QoI management allowing to unambiguously define system behavior for scenarios with single/multiple QoI requirement violations in different models of computation;(c) dynamically validate timing behavior of syst

关键词： Time timeliness performance quality-of-information model of computation moc model-driven design design patterns cyber-physical systems

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AN OPTIMAL IMPLEMENTATION OF BROADCASTING WITH SELECTIVE REDUCTION

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1993年第3期4卷 256-269页

作者： LINDON, LF AKL, SG Department of Vomputing and Information Science Queen's University Kingston ONT Canada Department of Computer and Information Science Queen's University Kingston ONT Canada

A new model of parallel computation called Broadcasting with Selective Reduction (BSR) can be viewed as a CRCW PRAM with one extension. An additional type of concurrent memory access is permitted in BSR, namely the BROADCAST instruction, by means of which all N processors may gain access to all M memory locations simultaneously for the purpose of writing. At each memory location, a subset of the incoming broadcast data is selected and reduced to one value finally stored in that location. For several problems, BSR algorithms are known which require fewer steps than the corresponding best-known PRAM algorithms, using the same number of processors. In this paper, we introduce a circuit to implement the BSR model, and show that, in size and depth, the circuit we present is of the same order as an optimal circuit implementing the PRAM. Thus, we claim that, if it is reasonable to assume that CRCW PRAM instructions execute in constant time, the assumption of a constant time BROADCAST instruction is no less reasonable.

关键词： BROADCAST CONCURRENT READ CONCURRENT WRITE INTERCONNECTION UNIT model of computation PARALLEL ALGORITHM PARALLEL RANDOM ACCESS MACHINE REDUCTION SELECTION

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Cake cutting: Explicit examples for impossibility results

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MATHEMATICAL SOCIAL SCIENCES 2019年 102卷 68-72页

作者： Cheze, Guillaume Univ Toulouse CNRS UPS IMTUMR 5219 F-31062 Toulouse 9 France

In this article we suggest a model of computation for the cake cutting problem. In this model the mediator can ask the same queries as in the Robertson-Webb model but he or she can only perform algebraic operations as in the Blum-Shub-Smale model. All existing algorithms described in the Robertson-Webb model can be described in this new model. We show that in this model there exist explicit couples of measures for which no algorithm outputs an equitable fair division with connected parts. We also show that there exist explicit sets of measures for which no algorithm in this model outputs a fair division which maximizes the utilitarian social welfare function. The main tool of our approach is Galois theory. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Fair division model of computation Galois theory

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PARALLEL computation AND CONFLICTS IN MEMORY ACCESS

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INFORMATION PROCESSING LETTERS 1982年第2期14卷 93-96页

作者： KUCERA, L Charles University Sokolovská 83 18600 Prague Czechoslovakia

Recent technological development has drawn the attention of many researchers in computer science to problems of parallel computation. Three possible generalizations of the rule that no 2 different processors may write simultaneously into the same memory location are shown: 1. weak conflict-resolution rule, in which simultaneous writing is permitted only to selected memory locations which can contain the numbers 0 or 1 only; 2. equality conflict-resolution rule, in which simultaneous writing into the same memory location is permitted, provided all processors involved store the same value; and 3. priority conflict-resolution rule, where processors are linearly ordered according to their priorities. It is apparent that each of these rules leads, in turn, to the next one. It is demonstrated, at the expense of the number of processors, that the computational power of all of these rules is equal in a certain sense. Five theorems are presented.

关键词： Parallel computation model of computation graph algorithms

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