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An extensible modeling methodology for embedded and cyber-physical system design

SIMULATION-TRANSACTIONS OF THE SOCIETY FOR MODELING AND SIMULATION INTERNATIONAL 2016年第8期92卷 771-794页

作者： Attarzadeh-Niaki, Seyed-Hosein Sander, Ingo Shahid Beheshti Univ Comp Engn Tehran Iran KTH Royal Inst Technol Elect Syst Design Stockholm Sweden

models are important tools to manage the increasing complexity of system design. The choice of a modeling language for constructing models governs what types of systems can be modeled, and which subsequent design activities can be performed. This is especially true for the area of embedded electronic and cyber-physical system design, which poses several challenging requirements of modeling and design methodologies. This article argues that the Formal System Design (ForSyDe) methodology with the necessary presented extensions fulfills these requirements, and thus qualifies for the design of tomorrow's systems. Based on the theory of models of computation and the concept of process constructors, heterogeneous models are captured in ForSyDe with formal semantics. A refined layer of the formalism is introduced to make its denotational-style semantics easy to implement on top of commonly used imperative languages, and an open-source realization on top of the IEEE standard language SystemC is presented. The introspection mechanism is introduced to automatically export an intermediate representation of the constructed models for further analysis/synthesis by external tools. Flexibility and extensibility of ForSyDe is emphasized by integrating a new timed model of computation without central synchronization, and by providing mechanisms for integrating foreign models, parallel and distributed simulation, modeling adaptive, data-parallel, and non-deterministic systems. A set of ForSyDe features is demonstrated in practice, and compared with similar approaches using a running example and two relevant case studies.

关键词： Cyber-physical systems formal modeling SystemC model introspection models of computation

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Modeling, Analysis, and Hard Real-Time Scheduling of Adaptive Streaming Applications

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2018年第11期37卷 2636-2648页

作者： Zhai, Jiali Teddy Niknam, Sobhan Stefanov, Todor Leiden Univ Leiden Inst Adv Comp Sci NL-2333 CA Leiden Netherlands

In real-time systems, the application's behavior has to be predictable at compile-time to guarantee timing constraints. However, modern streaming applications which exhibit adaptive behavior due to mode switching at run-time, may degrade system predictability due to unknown behavior of the application during mode transitions. Therefore, proper temporal analysis during mode transitions is imperative to preserve system predictability. To this end, in this paper, we initially introduce mode-aware data flow (MADF) which is our new predictable model of computation to efficiently capture the behavior of adaptive streaming applications. Then, as an important part of the operational semantics of MADF, we propose the maximum-overlap offset which is our novel protocol for mode transitions. The main advantage of this transition protocol is that, in contrast to self-timed transition protocols, it avoids timing interference between modes upon mode transitions. As a result, any mode transition can be analyzed independently from the mode transitions that occurred in the past. Based on this transition protocol, we propose a hard real-time analysis as well to guarantee timing constraints by avoiding processor overloading during mode transitions. Therefore, using this protocol, we can derive a lower bound and an upper bound on the earliest starting time of the tasks in the new mode during mode transitions in such a way that hard real-time constraints are respected.

关键词： Adaptive streaming applications hard real-time analysis and scheduling models of computation parameterized dataflow transition protocol

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The design of a multicore extension of the SPIN model checker

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IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 2007年第10期33卷 659-674页

作者： Holzmann, Gerard J. Bosnacki, Dragan CALTECH Jet Prop Labs Lab Reliable Software Pasadena CA 91109 USA Eindhoven Univ Technol NL-5600 MB Eindhoven Netherlands

We describe an extension of the SPIN model checker for use on multicore shared-memory systems and report on its performance. We show how, with proper load balancing, the time requirements of a verification run can, in some cases, be reduced close to N-fold when N processing cores are used. We also analyze the types of verification problems for which multicore algorithms cannot provide relief. The extensions discussed here require only relatively small changes in the SPIN source code and are compatible with most existing verification modes such as partial order reduction, the verification of temporal logic formulas, bitstate hashing, and hash-compact compression.

关键词： software/program verification model checking models of computation logics and meanings of programs distributed programming

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Designing, Modeling and Analysis of GALS Software Systems

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IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 2023年第8期49卷 3989-4003页

作者： Zhang, Weiyi Salcic, Zoran Malik, Avinash Univ Auckland Dept Elect Comp & Software Engn Auckland 1010 New Zealand

Designing software systems underpinned by a formal model of computation (MoC) is crucial for safety-critical, real-time and all industrial applications as it allows formal analysis of those designs and support for correct by design systems. In this paper, we focus on Globally Asynchronous Locally Synchronous (GALS) software systems and Coloured Petri Nets (CPNs) based approach to formally model and analyse GALS software systems specified in SystemJ GALS programming language. The approach translates SystemJ constructs into CPN modules and composes them into CPN GALS model based on control flow and concurrency specified in the SystemJ program. It preserves GALS MoC by automatically integrating synchronizer modules, asynchronous channel interface modules, and scheduling modules to result in the execution model of SystemJ program equivalent CPN. The created CPN GALS model allows system developers to verify the properties of the design formally with the use of computation Tree Logic (CTL). An industrial automation example is provided as a use case.

关键词： Formal models model checking models of computation petri nets systems and software

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Metamodeling: An Emerging Representation Paradigm for System-Level Design

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IEEE DESIGN & TEST OF COMPUTERS 2009年第3期26卷 54-69页

作者： Sangiovanni-Vincentelli, Alberto Shukla, Sandeep Kumar Sztipanovits, Janos Yang, Guang Mathaikutty, Deepak A. Univ Calif Berkeley Berkeley CA 94720 USA Virginia Polytech & State Univ Bradley Dept Elect & Comp Engn Blacksburg VA USA Vanderbilt Univ Nashville TN USA Natl Instruments Berkeley CA USA Intel Corp Microarchitecture Res Lab Santa Clara CA 95051 USA

Editor's note:The use of metamodeling in system design allows abstraction of concepts germane to a number of varying modeling domains, and provides the ability of exploiting meta-information for a variety of system design tasks such as analysis, verification, synthesis, and test generation. This article provides an overview of emerging metamodeling techniques and their applications.—Tim Cheng, IEEE Design & Test editor in chief

关键词： Metamodeling models of computation Design And Test IP Reuse Platform Based Design Mo C

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On the complexity of regular-grammars with integer attributes

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JOURNAL OF COMPUTER AND SYSTEM SCIENCES 2011年第2期77卷 393-421页

作者： Manna, M. Scarcello, F. Leone, N. Univ Calabria Dept Math I-87036 Arcavacata Di Rende CS Italy Univ Calabria Dept Elect Comp Sci & Syst I-87036 Arcavacata Di Rende CS Italy

Regular grammars with attributes overcome some limitations of classical regular grammars, sensibly enhancing their expressiveness. However, the addition of attributes increases the complexity of this formalism leading to intractability in the general case. In this paper, we consider regular grammars with attributes ranging over integers, providing an in-depth complexity analysis. We identify relevant fragments of tractable attribute grammars, where complexity and expressiveness are well balanced. In particular, we study the complexity of the classical problem of deciding whether a string belongs to the language generated by any attribute grammar from a given class C (call it PARSE(vertical bar C vertical bar)). We consider deterministic and ambiguous regular grammars, attributes specified by arithmetic expressions over {vertical bar vertical bar, +, -, divided by, %, *), and a possible restriction on the attributes composition (that we call strict composition). Deterministic regular grammars with attributes computed by arithmetic expressions over {vertical bar vertical bar, +. -, divided by, %} are P-complete. If the way to compose expressions is strict, they can be parsed in 1, and they remain tractable even if multiplication is allowed. Problem PARsE(vertical bar C vertical bar) becomes NP-complete for general regular grammars over {vertical bar vertical bar, -, divided by, %, *} with strict composition and for grammars over {vertical bar vertical bar, +, -, divided by, %} with unrestricted attribute composition. Finally, we show that even in the most general case the problem is in polynomial space. (C) (2)010 Elsevier Inc. All rights reserved.

关键词： Attribute grammars computational complexity models of computation

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Instrumentation-Driven Validation of Dataflow Applications

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2016年第3期84卷 383-397页

作者： Chukhman, Ilya Jiao, Yang Ben Salem, Haifa Bhattacharyya, Shuvra S. Univ Maryland Dept Elect Comp Engn College Pk MD 20742 USA Tech Univ Munich Elect Elect Comp Engn Munich Germany Univ Maryland Inst Adv Comp Studies College Pk MD 20742 USA Tampere Univ Technol Dept Pervas Comp Tampere Finland

Dataflow modeling offers a myriad of tools for designing and optimizing signal processing systems. A designer is able to take advantage of dataflow properties to effectively tune the system in connection with functionality and different performance metrics. However, a disparity in the specification of dataflow properties and the final implementation can lead to incorrect behavior that is difficult to detect. This motivates the problem of ensuring consistency between dataflow properties that are declared or otherwise assumed as part of dataflow-based application models, and the dataflow behavior that is exhibited by implementations that are derived from the models. In this paper, we address this problem by introducing a novel dataflow validation framework (DVF) that is able to identify disparities between an application's formal dataflow representation and its implementation. DVF works by instrumenting the implementation of an application and monitoring the instrumentation data as the application executes. This monitoring process is streamlined so that DVF achieves validation without major overhead. We demonstrate the utility of our DVF through design and implementation case studies involving an automatic speech recognition application, a JPEG encoder, and an acoustic tracking application.

关键词： Dataflow graphs models of computation Signal processing systems Design validation

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PAPIFY: Automatic Instrumentation and Monitoring of Dynamic Dataflow Applications Based on PAPI

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IEEE ACCESS 2019年 7卷 111801-111812页

作者： Madronal, Daniel Arrestier, Florian Sancho, Jaime Morvan, Antoine Lazcano, Raquel Desnos, Karol Salvador, Ruben Menard, Daniel Juarez, Eduardo Sanz, Cesar Univ Politecn Madrid Res Ctr Software Technol & Multimedia Syst CITSEM Madrid 28031 Spain Univ Rennes INSA Rennes CNRS IETR UMR 6164 F-35708 Rennes France

The widening of the complexity-productivity gap in application development witnessed in the last years is becoming an important issue for the developers. New design methods try to automate most designers tasks to bridge this gap. In addition, new Model of computations (MoCs), as those dataflow-based, ease the expression of parallelism within applications, leading to higher designer productivity. Rapid prototyping design tools offer fast estimations of the soundness of design choices. A key step when prototyping an application is to have representative performance indicators to estimate the validity of those design choices. Such indicators can be obtained using hardware information, while new libraries, e.g., Performance Application Programming Interface (PAPI), ease the access to such hardware information. In this work, PAPIFY toolbox is presented as a tool to perform automatic PAPI-based instrumentation of dynamic dataflow applications. It combines PAPIFY with a dataflow Y-chart based design framework, which is called PREESM, and its companion run-time reconfiguration manager, which is called Synchronous Parameterized and Interfaced Dataflow Embedded Runtime (SPiDER). PAPIFY toolbox accounts for an automatic code generator for static and dynamic applications, a dedicated library to manage the monitoring at run-time and two User Interfaces (UIs) to ease both the configuration and the analysis of the captured run-time information. Additionally, its main advantages are 1) its capability of adapting the monitoring according to the system status and 2) adaptation of the monitoring accordingly to application workload redistribution in run-time. A thorough overhead characterization using Sobel-morpho and Stereo-matching dataflow applications shows that PAPIFY run-time monitoring overhead is up to 10%.

关键词： Performance monitoring PMCs PAPI automatic code generation dataflow models of computation code instrumentation

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RDF: A Reconfigurable Dataflow Model of computation

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ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 2023年第1期22卷 1-30页

作者： Fradet, Pascal Girault, Alain Krishnaswamy, Ruby Nicollin, Xavier Shafiei, Arash Univ Grenoble Alpes INRIA CNRS Grenoble INPLIG Orange France Orange Labs 140 Ave Republ F-92320 Chatillon France

Dataflow models of computation (MoCs) are widely used in embedded systems, including multimedia processing, digital signal processing, telecommunications, and automatic control. In a dataflow MoC, an application is specified as a graph of actors connected by FIFO channels. One of the first and most popular dataflow MoCs, Synchronous Dataflow (SDF), provides static analyses to guarantee boundedness and liveness, which are key properties for embedded systems. However, SDF and most of its variants lack the capability to express the dynamism needed by modern streaming applications. In particular, the applications mentioned above have a strong need for reconfigurability to accommodate changes in the input data, the control objectives, or the environment. We address this need by proposing a new MoC called Reconfigurable Dataflow (RDF). RDF extends SDF with transformation rules that specify how and when the topology and actors of the graph may be reconfigured. Starting from an initial RDF graph and a set of transformation rules, an arbitrary number of new RDF graphs can be generated at runtime. A key feature of RDF is that it can be statically analyzed to guarantee that all possible graphs generated at runtime will be consistent and live. We introduce the RDF MoC, describe its associated static analyses, and present its implementation and some experimental results.

关键词： models of computation synchronous dataflow reconfigurable systems graph rewriting static analyses boundedness liveness

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Connectionist modal logic: Representing modalities in neural networks

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THEORETICAL COMPUTER SCIENCE 2007年第1-2期371卷 34-53页

作者： Garcez, Artur S. d'Avila Lamb, Luis C. Gabbay, Dov M. City Univ London Sch Informat Dept Comp London EC1V 0HB England Univ Fed Rio Grande do Sul Inst Informat BR-91501970 Porto Alegre RS Brazil Kings Coll London Dept Comp Sci London WC2R 2LS England

Modal logics are amongst the most successful applied logical systems. Neural networks were proved to be effective learning systems. In this paper, we propose to combine the strengths of modal logics and neural networks by introducing Connectionist Modal Logics (CML). CML belongs to the domain of neural-symbolic integration, which concerns the application of problem-specific symbolic knowledge within the neurocomputing paradigm. In CML, one may represent, reason or learn modal logics using a neural network. This is achieved by a Modalities Algorithm that translates modal logic programs into neural network ensembles. We show that the translation is sound, i.e. the network ensemble computes a fixed-point meaning of the original modal program, acting as a distributed computational model for modal logic. We also show that the fixed-point computation terminates whenever the modal program is well-behaved. Finally, we validate CML as a computational model for integrated knowledge representation and learning by applying it to a well-known testbed for distributed knowledge representation. This paves the way for a range of applications on integrated knowledge representation and learning, from practical reasoning to evolving multi-agent systems. (c) 2006 Elsevier B.V. All rights reserved.

关键词： models of computation neural-symbolic learning systems knowledge representation modal logics artificial neural networks

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