In the context of ongoing digitalization, ever more powerful, smaller electronic devices are required. These devices are usually intended to communicate wirelessly and require a high integration density for embedding ...
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ISBN:
(纸本)9781728175096
In the context of ongoing digitalization, ever more powerful, smaller electronic devices are required. These devices are usually intended to communicate wirelessly and require a high integration density for embedding in devices. With existing circuit board technologies these systems can be successfully implemented today. In the context of industrial IoT (Internet of Things), which increasingly demands individualized or customized solutions, these technologies are no longer fully suitable. Since these technologies require a high development effort as well as a complex and expensive manufacturing technology. As a result, these development and manufacturing processes are only economically interesting for high volumes in order to spread the high costs for development and set-up of the processes over many parts. Especially in a surrounding of Industrial Internet of Things (IIoT), many applications require shape adapted individual solutions in small quantities, e.g. retrofitting of existing machinery. In this area, MID technology offers plenty of potential for realising shape-adapted electronic devices with a high integration density. By using additive manufacturing processes, such as MID filament for fused deposition modelling, stereolithographic printing with subsequent coating with LDS lacquer or direct printing with a MID resin, these primary cost drivers can be eliminated. However, until now each MID component has been developed individually and the complete development cycle is performed repetitively for each new MID component. The complex 3D design process is a major obstacle to the efficient and cost-effective development of MID products in small batch sizes. Against the background of the high complexity of the MID manufacturing process and the associated inherent sources of error, new development approaches are needed. The here presented approach for a modular design methodology for an efficient development of 3D MID components simplifies and standardises this pr
Present Field Programmable Gate Array (FPGA) manufacturers incorporate multi-millions of logic resources which enables hardware designers to design applications extending to large scales. However, handling such applic...
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ISBN:
(纸本)9781728136325
Present Field Programmable Gate Array (FPGA) manufacturers incorporate multi-millions of logic resources which enables hardware designers to design applications extending to large scales. However, handling such applications by existing FPGA Computer Aided design (CAD) flow requires more improvement in terms of area, performance and power efficiency considerations. The current CAD flow requires the input design to be in Register Transfer Level (RTL). RTL input designs limit the design productivity only to hardware experts in performing analysis for various optimisations. Optimising RTI, designs manually are increasingly hard. High Level Synthesis (HLS) is an approach capable of increasing the design productivity of hardware applications compared to commonly used Hardware Description Languages (HDLs) and is known to be an intelligent approach for performing optimisations at a higher level of abstraction. In this paper, an approach that follows the HLS flow to cater to the mapping of FPGA applications in a power efficient manner using a communication aware partitioning strategy is proposed. From experiments, it was possible to achieve an average reduction of 8.39% routing thermal power and 3.34% total power using the proposed approach
This paper presents the design and implementation of a 3 kVA three-phase active T-type neutral-point clamped(NPC) inverter with GaN power devices for low-voltage microgrids. The designed inverter is used in a battery-...
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This paper presents the design and implementation of a 3 kVA three-phase active T-type neutral-point clamped(NPC) inverter with GaN power devices for low-voltage microgrids. The designed inverter is used in a battery-based energy system(BESS) for power conversion optimization in applications to low-voltage microgrids. A modulardesign method has been developed for the design and implementation of the AT-NPC inverter. Experimental verification has been carried out based on a 3-kW three-phase T-Type NPC grid-connected inverter. FPGA based digital control technique has been developed for the current control of the three-level three-phase grid inverter. A maximum efficiency of 98.49% has been achieved within a load range from 50% to 75%.
Quantum-dot cellular automata(QCA) is a promising nanotechnology,with the potential for faster speed,smaller size and lower power consumption than CMOS *** QCA circuit design,However,wire-crossing is an *** logic gate...
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Quantum-dot cellular automata(QCA) is a promising nanotechnology,with the potential for faster speed,smaller size and lower power consumption than CMOS *** QCA circuit design,However,wire-crossing is an *** logic gates(ULG) have stronger function than traditional logic *** paper begins with a review of *** a novel QCA optimal ULG.2 is obtained using a new algorithm and modulardesign *** circuits are implemented with the *** an example,finally,a full adder/subtraction is constructed by applying the *** simulation results confirm that all the proposed circuits not only hold correct logic function but also achieve a considerable wire-crossing count reduction in comparison to the other previous designs.
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