Microfluidic biochips are revolutionizing high-throughput DNA sequencing, immunoassays, and clinical diagnostics. As high-throughput bioassays are mapped to digital microfluidic platforms, the need for design automati...
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Microfluidic biochips are revolutionizing high-throughput DNA sequencing, immunoassays, and clinical diagnostics. As high-throughput bioassays are mapped to digital microfluidic platforms, the need for design automation techniques is being increasingly felt. Moreover, as most applications of biochips are safety-critical in nature, defect tolerance is an essential system attribute. Several synthesis tools have recently been proposed for the automated design of biochips from the specifications of laboratory protocols. However, only a few of these tools address the problem of defect tolerance. In addition, most of these methods do not consider the problem of droplet routing in microfluidic arrays. These methods typically rely on postsynthesis droplet routing to implement biochemical protocols. Such an approach is not only time consuming, but also imposes an undue burden on the chip user. Postsynthesis droplet routing does not guarantee that feasible droplet pathways can be found for area-constrained biochip layouts;nonroutable fabricated biochips must be discarded. We present a synthesis tool that integrates defect tolerance and droplet routing in the design flow. Droplet routability, defined as the ease with which droplet pathways can be determined, is estimated and integrated in the synthesis procedure. Presynthesis and postsynthesis defect-tolerance methods are also presented. We use a large-scale protein assay as a case study to evaluate the proposed synthesis method.
Microfluidic biochips are revolutionizing high-throughput DNA sequencing, immunoassays, and clinical diagnostics. As high-throughput bioassays are mapped to digital microfluidic platforms, the need for design automati...
详细信息
Microfluidic biochips are revolutionizing high-throughput DNA sequencing, immunoassays, and clinical diagnostics. As high-throughput bioassays are mapped to digital microfluidic platforms, the need for design automation techniques is being increasingly felt. Moreover, as most applications of biochips are safety-critical in nature, defect tolerance is an essential system attribute. Several synthesis tools have recently been proposed for the automated design of biochips from the specifications of laboratory protocols. However, only a few of these tools address the problem of defect tolerance. In addition, most of these methods do not consider the problem of droplet routing in microfluidic arrays. These methods typically rely on postsynthesis droplet routing to implement biochemical protocols. Such an approach is not only time consuming, but also imposes an undue burden on the chip user. Postsynthesis droplet routing does not guarantee that feasible droplet pathways can be found for area-constrained biochip layouts;nonroutable fabricated biochips must be discarded. We present a synthesis tool that integrates defect tolerance and droplet routing in the design flow. Droplet routability, defined as the ease with which droplet pathways can be determined, is estimated and integrated in the synthesis procedure. Presynthesis and postsynthesis defect-tolerance methods are also presented. We use a large-scale protein assay as a case study to evaluate the proposed synthesis method.
We describe algorithmic results on two crucial aspects of allocating resources on computational hardware devices with partial reconfigurability. By using methods from the field of computational geometry, we derive a m...
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We describe algorithmic results on two crucial aspects of allocating resources on computational hardware devices with partial reconfigurability. By using methods from the field of computational geometry, we derive a method that allows correct maintenance of free and occupied space of a set of n rectangular modules in time O(n log n);previous approaches needed a time of O(n(2)) for correct results and O(n) for heuristic results. We also show a matching lower bound of Omega(n log n), so our approach is optimal. We also show that finding an optimal feasible communication-conscious placement (which minimizes the total weighted Manhattan distance between the new module and existing demand points) can be computed with Theta(n log n). Both resulting algorithms are practically easy to implement and show convincing experimental behavior.
This paper discusses how to minimize the number of dissection lines regarded as wiring channels on a floorplan corresponding to a placement of n modules. In a floorplan (rectangular dissection), the number of dissecti...
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This paper discusses how to minimize the number of dissection lines regarded as wiring channels on a floorplan corresponding to a placement of n modules. In a floorplan (rectangular dissection), the number of dissection lines exceeds the number of rooms exactly by three. Since a floorplan obtained from a given module placement may have many empty rooms where no module is assigned, redundant wiring channels and wire bends may also be generated. Hence, in order to reduce redundant channels and wire bends, removal of empty rooms is required. For this purpose, we formulate a problem of obtaining a floorplan with the minimum possible empty rooms based on a given module placement. Then, we propose a method of removing as many redundant empty rooms as possible by merging dissection lines on a floorplan in O(n) time. The number of empty rooms in the resultant floorplan is reduced to n - [ root 4n - 1] or less.
In order to handle device matching for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis. In this paper, we deal with the module placement with symmetry constraints f...
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ISBN:
(纸本)0780387368
In order to handle device matching for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis. In this paper, we deal with the module placement with symmetry constraints for analog design using the Transitive Closure Graph-Sequence (TCG-S) representation. Since the geometric relationships of modules are transparent to TCG-S and its induced operations, TCG-S has better flexibility than previous works in dealing with symmetry constraints. We first propose the necessary and sufficient conditions of TCG-S for symmetry modules. Then, we propose a polynomial-time packing algorithm for a TCG-S with symmetry constraints. Experimental results show that the TCG-S based algorithm results in the best area utilization.
In this paper, we present an effective performance driven placement with global routing algorithm for macro cells. Our algorithm uses a hierarchical, divide and conquer, quad-partitioning approach. The quad-partitioni...
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In this paper, we present an effective performance driven placement with global routing algorithm for macro cells. Our algorithm uses a hierarchical, divide and conquer, quad-partitioning approach. The quad-partitioning routine uses the Tabu Search technique. Our algorithm uses the concept of proximity of regions to approximate the interconnection delays during lhe placement process. In addition, our algorithm can handle modules whose positions are fixed or are restricted to a particular subregion on the layout frame. Our experimental results indicate the superiority of our placement method in terms of quality of solution and run time when compared to Lin and Du (1990).
Given a collection R of n (= M X N) rectangles, we wish to pack it into M rows and N columns as the elements of an M X N matrix. The height of a row is defined to be the height of the tallest rectangle in that row, an...
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Given a collection R of n (= M X N) rectangles, we wish to pack it into M rows and N columns as the elements of an M X N matrix. The height of a row is defined to be the height of the tallest rectangle in that row, and the width of a column is defined to be the width of the widest rectangle in that column. The cost of a packing is the sum of the heights of the M rows plus the sum of the widths of the N columns. The oriented aligned rectangle packing problem is to find a packing with the minimum cost. In this paper we present an O(n) time algorithm and an O(n2) time algorithm for two non-trivial special cases. We also show how to extend the algorithms to handle other cost functions.
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