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module selection in microarchitectural synthesis for multiple critical constraint satisfaction

VLSI DESIGN 1997年第2期5卷 167-182页

作者： Harris, IG Orailoglu, A UNIV CALIF SAN DIEGO DEPT COMP SCI & ENGNLA JOLLACA 92093

Accurate design descriptions during synthesis allow efficient use of resources. The appropriate use of distinct implementations of RTL operators helps generate optimal VLSI designs. The system presented here utilizes libraries composed of multiple modules with identical functionality, but distinct performance and area characteristics. Such libraries allow the generation of an accurate estimate of the area and delay of the final design during synthesis. Full use of the module selection capability is possible by allowing the user to specify a total area limit rather than a detailed allocation. Consequently, tradeoffs between different allocations can be fully explored. Scheduling, module selection, and allocation are performed simultaneously to achieve optimal use of area and delay, and to facilitate the incorporation of lower level design considerations into behavioral synthesis. Synthesis decisions are made in a time-constrained and area-constrained fashion, by using both constraints to identify and avoid infeasible design possibilities. module selection, scheduling, and allocation for pipelined designs is also implemented. Experimental results show that the use of module selection and rime-and-area-constrained synthesis results in an area/delay design curve which is superior to the results of traditional systems.

关键词： module selection behavioral synthesis scheduling allocation constraint satisfaction estimation

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Ontology-based module selection in the design of reconfigurable machine tools

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JOURNAL OF INTELLIGENT MANUFACTURING 2020年第2期31卷 301-317页

作者： Ming, Zhenjun Zeng, Cong Wang, Guoxin Hao, Jia Yan, Yan Beijing Inst Technol Sch Mech Engn 5 Zhongguancun South St Beijing 100081 Peoples R China

Reconfigurable machine tools (RMTs) are important equipment for enterprises to cope with ever-changing markets because of their flexibility. In design of such equipment, selection of appropriate modules is a very critical decision factor to effectively and efficiently satisfy manufacturing requirements. However, the selection of appropriate modules is a challenging task because it is a multi-domain mapping process relying heavily on experts' domain knowledge, which is usually unstructured and implicit. To effectively support RMT designers, an ontology-based RMT module selection method is proposed. First, a knowledge base is built by development of an ontology to formally represent the taxonomy, properties, and causal relationships of/among three domain core concepts, namely, machining feature, machining operation, and RMT module involved in RMT design. Second, a four-step sequential procedure is established to facilitate the utilization of encoded knowledge from a knowledge base to aid in the selection of appropriate RMT modules. The procedure takes a given part family as the input, automatically infers the required machining operations as well as the RMT modules through rule-based reasoning, and eventually forms a set of RMT configurations that are capable of machining the part family as the output. Finally, the efficacy of the ontology-based RMT module selection method is demonstrated using a plate family manufacturing example. Results show that the approach is effective to support designers by appropriately and rapidly selecting modules and generating configurations in RMT design.

关键词： Reconfigurable machine tool Design module selection Ontology SWRL rule Knowledge base

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ILP-based cost-optimal DSP synthesis with module selection and data format conversion

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1998年第4期6卷 582-594页

作者： Ito, K Lucke, LE Parhi, KK Saitama Univ Dept Elect & Elect Syst Urawa Saitama 3388570 Japan Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA

In high-level synthesis, a data how graph (DFG) description of an algorithm is mapped onto a register transfer level description of an architecture, Each node of the DFG is scheduled to a specific time and allocated to a processor. In this paper, we present new integer linear programming (ILP) models which generate a blocked schedule for a DFG with automatic retiming, pipelining, and unfolding while performing module selection and data format conversion. A blocked schedule is a schedule which overlaps multiple iterations of the DFG to guarantee a processor optimal schedule. During module selection an appropriate processor is chosen from a library of processors to construct a cost optimal architecture. Furthermore, we also include the cost and latency of data format conversions between processors of different implementation styles, We also present a new formulation for minimizing the unfolding factor of the blocked schedule. The approach presented in this paper is the only systematic approach proposed so far to include implicit unfolding and to perform synthesis using nonuniform processor styles and data format converters.

关键词： data format conversion high-level synthesis integer linear programming module selection time-constrained scheduling

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Optimal module selection for preliminary design of reconfigurable machine tools

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JOURNAL OF MANUFACTURING SCIENCE AND ENGINEERING-TRANSACTIONS OF THE ASME 2005年第1期127卷 104-115页

作者： Chen, L Xi, FF Macwan, A Univ Toronto Design & Mfg Integrat Lab Dept Mech & Ind Engn Toronto ON Canada Ryerson Univ Dept Aerosp Engn Toronto ON Canada

Presented in this paper is a feature-based method for selecting an optimal (minimum yet sufficient) set of modules necessary to form a reconfigurable machine tool for producing a part family. This method consists of two parts. In the first part, a feature-module database is created to form a selection space, where the machinable geometric features identified in STEP are defined as functional requirements (FR's) and the structural component modules derived from the conventional machine tools as design parameters (DP's). An inner FR-to-DP mapping mechanism within the database is based on the "Membership Grade Matrix, " which defines metrics to quantify the degree of association between a FR and a DR Within the confines of the selection space built upon this FR-DP database, the second part of the method involves a two-step procedure for module selection. The first step is to select the modules from this space to construct all the required individual configurations of the reconfigurable machine tool. The second step is to maximize the number of common modules among the originally selected modules through re-selection. A case study on designing a reconfigurable machine tool dedicated to a given family of die molds is conducted and discussed.

关键词： module selection reconfiguration machine tools design machinable features

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REGISTER-TRANSFER module selection FOR SUBMICRON ASIC DESIGN

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1995年第3期E78D卷 252-255页

作者： MOSHNYAGA, VG MORI, Y TAMARU, K Kyoto Univ Japan

In order to shorten the time-to-market, Application-Specific Integrated Circuits (ASIC's) are designed from a library of pre-defined layout implementations for register-transfer modules such as multipliers, adders, RAM, ROM, etc. Current approaches to selecting the implementations from the library usually deal with their timing-area estimates and do not consider delay of the intermodule wiring. However, as sub-micron design rules are utilized for IC fabrication, wiring delay becomes comparable to the functional unit delay and can not longer be ignored even in register-transfer synthesis. In this paper we propose an algorithm that combines module selection with Performance-Driven module placement and reduces an impact of wiring on sub-micron ASIC performance. The algorithm not only efficiently exploits multiple module realizations in the design library, but also finds the module placement which minimizes wiring delay. Experimental results on several benchmarks show that considering both module and wiring issues, more than 30% reduction of the total circuit delay can be achieved.

关键词： module selection REGISTER TRANSFER SYNTHESIS

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FPGA pipeline synthesis design exploration using module selection and resource sharing

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2007年第2期26卷 254-265页

作者： Sun, Welson Wirthlin, Michael J. Neuendorffer, Stephen Xilinx Res Labs San Jose CA 95124 USA

The primary goal during synthesis of digital signal processing (DSP) circuits is to minimize the hardware area while meeting a minimum throughput constraint. In field-programmable gate array (FPGA) implementations, significant area savings can be achieved by using slower, more area-efficient circuit modules and/or by time-multiplexing faster, larger circuit modules. Unfortunately, manual exploration of this design space is impractical. In this paper, we introduce a design exploration methodology that identifies the lowest cost FPGA pipelined implementation of an untimed synchronous data-flow graph by combined module selection with resource sharing under the context of pipeline scheduling. These. techniques are applied together to minimize the area cost of the FPGA implementation while meeting a user-specified minimum throughput constraint. Two different algorithms are introduced for exploring the large design space. We show that even. for small DSP algorithms, combining these techniques can offer significant area savings relative to applying any of them alone.

关键词： data-path synthesis module selection pipeline scheduling resource sharing

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FPGA pipeline synthesis design exploration using module selection and resource sharing

FPGA pipeline synthesis design exploration using module sele...

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International Symposium on Field-Programmable Gate Arrays

作者： Sun, Welson Wirthlin, Michael J. Neuendorffer, Stephen Xilinx Res Labs San Jose CA 95124 USA

关键词： data-path synthesis module selection pipeline scheduling resource sharing

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A simultaneous module selection, scheduling, and allocation method considering operation chaining with multi-functional units

A simultaneous module selection, scheduling, and allocation ...

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19th Workshop on Circuits and Systems

作者： Sadakata, Tsuyoshi Matsunaga, Yusuke Kyushu Univ Grad Sch Informat Sci & Elect Engn Dept Comp Sci & Commun Engn Fukuoka 8160395 Japan Kyushu Univ Fac Informat Sci & Elect Engn Dept Comp Sci & Commun Engn Fukuoka 8160395 Japan

A Multi-Functional unit has several functions and these can be changed with a control signal. For High-Level Synthesis, using Multi-Functions units in operation chaining make it possible to obtaining the solution with the same number of control steps and less resources compared to that without them. This paper proposes an operation chaining method considering Multi-Functional units. The method formulates module selection, scheduling, and functional unit allocation with operation chaining as a 0/1 integer linear problem and obtains optimal solution with minimum number of control steps under area and clock-cycle type constraints. The first contribution of this paper is to propose the global search for operation chaining with Multi-Functional units having multiple outputs as well as with single output. The second contribution is to condier the area constraint as a resource constraint instead (if the type and number of functional units. Experimental results show that chaining with Multi-Functional units is effective and the proposed method is useful to evaluate heuristic algorithms.

关键词： high-level synthesis scheduling allocation module selection operation chaining integer linear programming

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module selection using manufacturing information

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1998年第12期E81A卷 2576-2584页

作者： Tomiyama, H Yasuura, H Kyushu Univ Grad Sch Informat Sci & Elect Engn Dept Comp Sci & Commun Engn Kasuga Fukuoka 8168580 Japan

Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the process fluctuation has rarely been considered in most of existing high-level synthesis systems. This paper presents a new approach to module selection in high-level synthesis, which exploits the difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, we propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds optimal module selections which would not have been explored without manufacturing information.

关键词： high-level synthesis module selection manufacturability yield

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Research on module selection Method in the Modular Design of CNC Machine Tool

Research on Module Selection Method in the Modular Design of...

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1st International Workshop on Hydraulic Equipment and Support Systems for Mining (IWHEM 2012)

作者： Zhang, Chaobiao Wang, Pengjia Sheng, Zhongqi Liu, Yongxian Northeastern Univ Sch Mech Engn & Automat Shenyang 110004 Peoples R China

ISBN: (纸本)9783037855553

In modular design of product, seeking the optimal matching module and realize the optimal combination of product configuration is very important. This paper analyzes the module selection strategy in modular design of CNC machine tool, give the module selection algorithm. Relevant theory of fuzzy similarity optimal ratio is introduced on the search for the optimal matching module, and module selection system is developed by MATLAB. Finally, through an example, prove the effectiveness of the proposed algorithm and convenience of module selection system.

关键词： Modular design module selection Fuzzy similarity priority ratio Select system

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