检索结果-内蒙古大学图书馆

4th International Conference on Computing, Communications and Networking Technologies (ICCCNT)

作者： Kakde, Sandeep Somulu, G. Zode, Pravin Yashwantrao Chavan Coll Engn Dept Elect Engn Nagpur Maharashtra India

ISBN: (纸本)9781479939251

Modular multiplication finds the major role in RSA Cryptography and Elliptical Curve Cryptography. Timing analysis measures the delay along the various timing paths and verifies the performance and operation of the design. We have implemented a 256-bit Modular multiplier using montgomery Reduction algorithm in VHDL. The output of the montgomery multiplier is Z= X*Y R-1 mod M. Both RSA key generation component and data encryption component are too big to fit into a single Altera Cyclone II Device on Field Programmable platform, so that we are unable to test them in real hardware. However, each sub-component was simulated in Model-Sim SE 6.0 and Altera Quartus II 8.0 and proved functionally correct.

关键词： Carry Save Adder montgomery algorithm RSA Cryptography Modular Arithmetic

来源：评论

学校读者我要写书评

暂无评论

Hardware Architecture for RSA Cryptography Based on Residue Number System

引用

Transactions of Tianjin University 2012年第4期18卷 237-242页

作者：郭炜刘亚灵白松辉魏继增孙达志 School of Computer Science and Technology Tianjin University

A parallel architecture for efficient hardware implementation of Rivest Shamir Adleman(RSA) cryptography is *** number system(RNS) is introduced to realize high parallelism,thus all the elements under the same base are independent of each other and can be computed in ***,a simple and fast base transformation is used to achieve RNS montgomery modular multiplication algorithm,which facilitates hardware *** on transport triggered architecture(TTA),the proposed architecture is designed to evaluate the performance and feasibility of the *** these optimizations,a decryption rate of 106 kbps can be achieved for 1 024-b RSA at the frequency of 100 MHz.

关键词： residue number system RSA cryptography montgomery algorithm computer architecture parallelalgorithm

来源：评论

学校读者我要写书评

暂无评论

An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized montgomery Operations for DF-ECC Processor

An Efficient Countermeasure against Correlation Power-Analys...

引用

14th International Workshop on Cryptographic Hardware and Embedded Systems (CHES)

作者： Lee, Jen-Wei Chung, Szu-Chi Chang, Hsie-Chia Lee, Chen-Yi Natl Chiao Tung Univ Dept Elect Engn Hsinchu Taiwan Natl Chiao Tung Univ Inst Elect Hsinchu Taiwan

ISBN: (纸本)9783642330278;9783642330261

Correlation power-analysis (CPA) attacks are a serious threat for cryptographic device because the key can be disclosed from data-dependent power consumption. Hiding power consumption of encryption circuit can increase the security against CPA attacks, but it results in a large overhead for cost, speed, and energy dissipation. Masking processed data such as randomized scalar or primary base point on elliptic curve is another approach to prevent CPA attacks. However, these methods requiring pre-computed data are not suitable for hardware implementation of real-time applications. In this paper, a new CPA countermeasure performing all field operations in a randomized montgomery domain is proposed to eliminate the correlation between target and reference power traces. After implemented in 90-nm CMOS process, our protected 521-bit dual-field elliptic curve cryptographic (DF-ECC) processor can perform one elliptic curve scalar multiplication (ECSM) in 4.57ms over GF(p(521)) and 2.77ms over GF(2(409)) with 3.6% area and 3.8% power overhead. Experiments from an FPGA evaluation board demonstrate that the private key of unprotected device will be revealed within 10(3) power traces, whereas the same attacks on our proposal cannot successfully extract the key value even after 10(6) measurements.

关键词： Elliptic curve cryptography (ECC) side-channel attacks power-analysis attacks montgomery algorithm

来源：评论

学校读者我要写书评

暂无评论

A Novel Architecture for RSA based on Residue Number System

A Novel Architecture for RSA based on Residue Number System

引用

2011 International Conference on Computers, Communications, Control and Automation

作者： Yaling Liu Wei Guo Jiao Su Jizeng Wei Dazhi Sun School of Computer Science and Technology Tianjin University

In this paper, an architecture of hardware implementation for RSA is proposed. Residue Number System(RNS) is introduced to get highly parallelism, in which all the elements are independent to each other and can be computed in parallel. Moreover, a simple and fast base transformation method is used to achieve RNS montgomery modular multiplication algorithm, which facilitates hardware implementation. A novel architecture, based on Transport Triggered Architecture(TTA), is designed to confirm the performance and feasibility of the algorithm. With these optimizations, a decryption rate of 227 Kbps can be achieved for 1024-bit RSA at the frequency of 100 MHz.

关键词： residue number system(RNS) RSA montgomery algorithm transport triggered architecture(TTA) CRT

来源：评论

学校读者我要写书评

暂无评论

An Optimized Architecture to Speed Up the montgomery Modular

An Optimized Architecture to Speed Up the Montgomery Modular

引用

2011 International Conference on Computers, Communications, Control and Automation

作者： Zongbin Liu Jiwu Jing Luning Xia Wuqiong Pan LOIS GUCAS LOIS GUCAS

Security is an important aspect in many application of modern information technology, including electronic commerce, virtual private networks, secure internet access and so on. In these application areas public-key cryptography plays a very important role. At present many public key encryption schemes, including ECC, RSA, use modular exponentiation of large numbers. However, the large number modular exponentiation is very slow. There are many methods have been proposed to speed up the modular exponentiation,among which the montgomery algorithm is widely used. This contribution proposes a novel architecture which is optimized for modern field programmable gate arrays(FPGAs). This optimized architecture based on the new architecture of the modern FPGA is used to speed up the montgomery modular algorithm. Our architecture is based on the dedicated resources on FPGA, and it uses high radix montgomery algorithm to reduce the clock consumption of the algorithm. In our evaluation, the 256-bit montgomery multiplication only needs52-clock, and the critical path is only 66-bit adder. Compared with the previous works, our architecture can run under high frequency and need less clock cycles. The new architecture has been verified by modeling it in Verilog-HDL, implementing it using Xilinx Virex-5 110 T FPGA.

关键词： montgomery algorithm modular multiplier

来源：评论

学校读者我要写书评

暂无评论

Low Complexity Digit Serial Systolic montgomery Multipliers for Special Class of GF(2^m)

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2010年第5期18卷 847-852页

作者： Talapatra, Somsubhra Rahaman, Hafizur Mathew, Jimson Bengal Engn & Sci Univ Dept Informat Technol Sibpur 711103 India Univ Bristol Dept Comp Sci Bristol BS8 1UB Avon England

montgomery algorithm for modular multiplication with a large modulus has been widely used in public key cryptosystems for secured data communication. This paper presents a digit-serial systolic multiplication architecture for all-one polynomials (AOP) over GF(2(m)) for efficient implementation of montgomery Multiplication (MM) algorithm suitable for cryptosystem. Analysis shows that the latency and circuit complexity of the proposed architecture are significantly less than those of earlier designs for same classes of polynomials. Since the systolic multiplier has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The proposed multipliers have clock cycle latency of (2N - 1), where N = [m/L], m is the word size and is the digit size. No digit serial systolic architecture based on MM algorithm over GF(2(m)) is reported before. The architecture is also compared to two well known digit serial systolic architectures.

关键词： Digit-serial finite field montgomery algorithm multiplication systolic array VLSI

来源：评论

学校读者我要写书评

暂无评论

An efficient montgomery exponentiation algorithm by using signed-digit-recoding and folding techniques

引用

APPLIED MATHEMATICS AND COMPUTATION 2007年第1期185卷 31-44页

作者： Lou, Der-Chyuan Lai, Jui-Chang Wu, Chia-Long Chang, Te-Jen Chinese AF Inst Technol Dept Aviat & Commun Electron Kaohsiung 82047 Taiwan Natl Def Univ Chung Cheng Inst Technol Dept Elect Engn Tao Yuan 33509 Taiwan

The motivation for designing fast modular exponentiation algorithms comes from their applications in computer science. In this paper, a new CSD-EF montgomery binary exponentiation algorithm is proposed. It is based on the montgomery algorithm using the canonical-signed-digit (CSD) technique and the exponent-folding (EF) binary exponentiation technique. By using the exponent-folding technique of computing the common parts in the folded substrings, the same common part in the folding substrings can be simply computed once. We can thus improve the efficiency of the binary exponentiation algorithm by decreasing the number of modular multiplications. Moreover, the "signed-digit representation" has less occurrence probability of the nonzero digit than binary number representation. Taking this advantage, we can further effectively decrease the amount of modular multiplications and we can therefore decrease the computational complexity of modular exponentiation. As compared with the Ha-Moon's algorithm 1.261718m multiplications and the Lou-Chang's algorithm 1.375m multiplications, the proposed CSD-EF montgomery algorithm on average only takes 0.5m multiplications to evaluate modular exponentiation, where m is the bit-length of the exponent. (c) 2006 Elsevier Inc. All rights reserved.

关键词： montgomery algorithm modular exponentiation exponent-folding technique algorithm analysis canonical-signed-digit recoding

来源：评论

学校读者我要写书评

暂无评论

Scalable hardware implementing high-radix montgomery multiplication algorithm

引用

JOURNAL OF SYSTEMS ARCHITECTURE 2007年第2-3期53卷 117-126页

作者： Bernard, F. Thales Commun France F-92704 Colombes France

This paper presents a new scalable hardware implementing modular multiplication. A high radix montgomery multiplication algorithm without final subtraction is used to perform this operation. An alternative proof for the final montgomery multiplication by 1, removing the condition on the modulus, is given. This hardware fits in any chip area and is able to work with any size of modulus. Unlike other scalable designs only one cell is used. This cell contains standard and well optimized digit multiplier and adder. Time-area trade-offs are also available before hardware synthesis for differents sizes of internal data path. The pipeline architecture of the multiplier component increases the clock frequency and the throughput. Time-area trade-offs are analyzed in order to make the best choice for given time and area constraints. This architecture seems to provide a better time-area compromise than previous scalable hardware. (c) 2006 Elsevier B.V. All rights reserved.

关键词： modular multiplication conventional multiplier montgomery algorithm high radix pipeline

来源：评论

学校读者我要写书评

暂无评论

Unified Digit Serial Systolic montgomery Multiplication Architecture for Special Classes of Polynomials over GF(2^m)

Unified Digit Serial Systolic Montgomery Multiplication Arch...

引用

13th Euromicro Conference on Digital System Design on Architectures, Methods and Tools

作者： Talapatra, Somsubhra Rahaman, Hafizur Saha, Samir K. Bengal Engn & Sci Univ Dept Informat Technol Sibpur India

ISBN: (纸本)9780769541716

This paper presents an unified digit-serial systolic multiplication architecture for all-one polynomials (AOP) and trinomial over GF(2(m)) for efficient implementation of montgomery Multiplication (MM) algorithm suitable for cryptosystem. This is the first reported unified digit serial systolic digit level pipelined MM architecture for AOP and trinomials over GF(2). Analysis shows that the latency and circuit complexity of the proposed architecture are significantly less compared to earlier design for same class of polynomials. The proposed multiplier has clock cycle latency of (2N) where N=[m/L], m is the word size and L is the digit size.

关键词： Galois Field multiplication digit-serial systolic array VLSI montgomery algorithm

来源：评论

学校读者我要写书评

暂无评论

A 3-Stage Pipelined Large Integer Modular Arithmetic Unit for ECC

A 3-Stage Pipelined Large Integer Modular Arithmetic Unit fo...

引用

1st International Symposium on Information Engineering and Electronic Commerce

作者： Duan Cheng-hua Liu Yi Chen Yong-tao Chinese Acad Sci Sch Informat Sci & Engn Grad Univ Beijing Peoples R China

ISBN: (纸本)9780769536866

Large integer modular multiptication and modular addition/subtraction are basic operations in Elliptic Curve Cryptography (ECC). Traditionally, systolic array was used to implement modular multiplication. It is not efficient because of data dependency between neighbor processing elements (PEs). In this paper, we propose a compact Modular Multiplication and Addition Unit (MMAU) specific for ECC by dividing an improved montgomery Modular Multiplication (MMM) algorithm into three parts, mapping them correspondingly to a 3-stage pipelined circuit and adding a small amount of hardware to the third stage of the pipeline for implementing modular addition/subtraction without affecting the performance of MMM. The MMAU computes one modular multiplication and one modular addition/subtraction in every 3(n+7) clock cycles for n-bit operands. When the pipeline is fully utilized, the MMAU can generate a result at every n+7 cycles. The experimental results show that our scheme achieves a higher throughput with less resource compared with existed ones.

关键词： Symmetric elliptic curve cryptography (ECC) pipelining technique montgomery algorithm modular addition/subtractionIntroduction

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：