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Fast implementation of digital signature system based on RSA algorithm

Jisuanji Gongcheng/Computer Engineering 2006年第3期32卷 156-157+160页

作者： Zhang, Hua Cui, Huijuan Tang, Kun State Key Laboratory on Microwave and Digital Communications Department of Electronic Engineering Tsinghua University Beijing 100084 China

Different from binary method of modular exponentiation, the article introduces a faster and more effective sliding window method combined with montgomery algorithm and the CRT (Chinese Remainder Theory). The flow charts of signature and verification are also given. The experiment result shows that sliding window method is 22.3% faster than the binary method. Meanwhile, it takes only 28 ms to do a 1024 bit signature.

关键词： Chinese remainder theory (CRT) Modular exponentiation montgomery algorithm RSA algorithm

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Design optimization of a high-speed, area-efficient and low-power montgomery modular multiplier for RSA algorithm

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IEICE TRANSACTIONS ON ELECTRONICS 2005年第4期E88C卷 576-581页

作者： Masui, S Mukaida, K Takenaka, M Torii, N Fujitsu Labs Ltd Kawasaki Kanagawa 2118588 Japan Fujitsu Ltd Kawasaki Kanagawa 2118588 Japan

High-speed, area-efficient, and low-power montgomery modular multipliers for RSA algorithm have been developed for digital signature and user authentication in high-speed network systems and smart card LSIs. The multiplier-accumulators (MAC) in the developed montgomery modular multipliers have a non-identical multiplicand/multiplier word length organization. This organization can eliminate the bandwidth bottleneck associated with a data memory, and enables to use a single-port memory for area and power reductions. The developed MAC is faster than the conventional identical word length organization due to the shortened critical path. For smart card applications, an area-efficient architecture with 42 kgates can produce 1.2 digital signatures in a second for 2,048-bit key length with the power consumption of 6.8 mW.

关键词： public key cryptosystem RSA algorithm montgomery algorithm modular multiplication multiplier-accumulator

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A 1024-bit RSA cryptosystem hardware design based on modified montgomery's algorithm 5

A 1024-bit RSA cryptosystem hardware design based on modifie...

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5th International Conference on ASIC

作者： Gong, PJ Guo, L Bai, XF Univ Sci & Technol China Dept Elect Sci & Technol Hefei 230026 Anhui Peoples R China

ISBN: (纸本)078037889X

A new version of montgomery's algorithm for modular multiplication of large integers is presented in this paper. And a 64-bit parallel cam, look-ahead binary adder implemented by SRCMOS (self-resetting CMOS) circuits substitutes for the CPA and one of the two CSAs, which are needed in the previous implementation. And then we can get the modular multiplication result after the loop without the final comparison achieved by making the size of r two bits larger than that of N. In addition. SRCMOS circuits have lower power, faster switching speed and less area than equivalent static CMOS implementations, so we can get a high performance RSA cryptosystem.

关键词： cryptography adders logic design CMOS integrated circuits digital arithmetic montgomery algorithm modular multiplication carry look-ahead binary adder SRCMOS self-resetting CMOS CMOS circuits RSA cryptosystem hardware design

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Digit-serial-in-serial-out systolic multiplier for montgomery algorithm

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INFORMATION PROCESSING LETTERS 2002年第2期82卷 65-71页

作者： Lee, KJ Kim, KW Yoo, KY Kyungpook Natl Univ Dept Comp Engn Buk Ku Taegu 702701 South Korea

This paper proposes a systematic design of a digit-serial-in-serial-out systolic multiplier for the efficient implementation of the montgomery algorithm in an RSA cryptosystem. For processing speed, the proposed multiplier can also accommodate bit-level pipelining, thereby achieving sample speeds comparable to bit-parallel multipliers with a lower area. If the appropriate digit-size is chosen, the proposed architecture can meet the throughput requirement of a specific application with minimum hardware. The new digit-serial systolic multiplier is highly regular, nearest-neighbor connected, and thus well suited for VLSI implementation. (C) 2002 Elsevier Science B.V All rights reserved.

关键词： cryptography public key cryptosystem montgomery algorithm

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Normal basis multiplication algorithm for GF(2ⁿ)

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ELECTRONICS LETTERS 2004年第18期40卷 1112-1113页

作者： Fan, H Dai, Y Tsing Hua Univ Dept Comp Sci Beijing 100084 Peoples R China

A normal basis multiplication algorithm is presented. Its complexity depends on the multiplicative order ofthe normal element.

关键词： montgomery algorithm Microprocessor chips Logic and switching circuits Logic circuits Cryptography cryptography Microprocessors and microcomputers Computational complexity polynomials multiplying circuits microprocessor chips normal basis multiplication algorithm Interpolation and function approximation (numerical analysis) Cryptography theory GF(2n) computational complexity

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Fast reconfigurable systolic hardware for modular multiplication and exponentiation

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JOURNAL OF SYSTEMS ARCHITECTURE 2003年第7-9期49卷 387-396页

作者： Nedjah, N Mourelle, LD Univ Estado Rio De Janeiro Dept Syst Engn & Computat Fac Engn BR-20550900 Rio De Janeiro Brazil

Modular multiplication and modular exponentiation are fundamental operations in most public-key cryptosystems such as RSA. In this paper, we propose a novel implementation of these operations using systolic arrays based architectures. For this purpose, we use the montgomery algorithm to compute the modular product and the left-to-right binary exponentiation method to yield the modular power. In the proposed design, we invest hardware area in the hope of improving encryption/decryption throughput. Our implementation improves time requirement as well as the time area factor when compared that of Blum's and Paar's. (C) 2003 Elsevier B.V. All rights reserved.

关键词： RSA-cryptosystems montgomery algorithm binary exponentiation

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A novel ASIC implementation of RSA algorithm 5

A novel ASIC implementation of RSA algorithm

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5th International Conference on ASIC

作者： Zhu, KJ Xu, K Wang, Y Min, H Fudan Univ ASIC & Syst State Key Lab Shanghai 200433 Peoples R China

ISBN: (纸本)078037889X

In this paper, a novel ASIC implementation of RSA algorithm is presented, By utilizing Yang's modified montgomery algorithm, the over-large residue problem is eliminated. The multiplication and montgomery modular reduction in modular multiplication are handled identically to minimize hardware cost. Microprogrammed control makes the architecture very flexible to support variable key lengths. These features make the chip very suitable for smart card applications. A RSA coprocessor based on the new architecture has been fabricated with 0.5 mu m CMOS cell library. The coprocessor has 14 K gate counts and 3 mm(2) die size with a maximum clock frequency of 40 MHz, which takes about 325 ms to encrypt/decrypt 1024-bit data.

关键词： application specific integrated circuits microprocessor chips hardware-software codesign digital arithmetic CMOS digital integrated circuits smart cards ASIC RSA algorithm montgomery algorithm over-large residue problem modular reduction modular multiplication hardware cost microprogrammed control smart card RSA coprocessor CMOS cell library clock frequency 0.5 microns 40 MHz 325 ms

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Area and time efficient modular multiplication of large integers

Area and time efficient modular multiplication of large inte...

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14th IEEE International Conference on Application-Specific Systems, Architectures and Processors

作者： Bunimov, V Schimmler, M Tech Univ Braunschweig Inst Comp & Commun Network Engn D-3300 Braunschweig Germany

ISBN: (纸本)076951992X

A new modular multiplication algorithm and its corresponding architecture is presented. It is optimised with respect to hardware complexity and latency. Based on the data flow of the well known interleaved modular multiplication the product of two n-bit-integers X and Y modulo M is computed by n iterations of a simple loop. The loop consists of one single carry save addition, a comparison of constant complexity, and a table lookup, where the table contains 6 precomputed values and two constants. By this construction the arithmetical complexity of the modular multiplication is reduced to n additions without carry propagation in total which leads to a speedup of at least two in comparison to all methods previously known. The paper consists of a first algorithm A2 implementing the new idea of combining carry save addition and constant time comparison. A2 is not optimal with respect to area and time. Its correctness is proven. By use of a small amount of precomputing the loop of A2 can be modified such that the effort within the loop is minimised. This leads to the algorithm A3. Its verification concludes the paper.

关键词： Modular multiplication montgomery algorithm interleaved modular multiplication MSB-first arithmetic carry save addition redundant number arithmetic

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Design of a linear systolic array for computing modular multiplication and squaring in GF(2^m)

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COMPUTERS & MATHEMATICS WITH APPLICATIONS 2001年第1-2期42卷 231-240页

作者： Lee, WH Lee, KJ Yoo, KY Kyungpook Natl Univ Dept Comp Engn Taegu South Korea

One of the main operations for the public key cryptosystem is the modular expoaentiation. In this paper, we analyze the montgomery's algorithm and design a linear systolic array for performing both modular multiplication and modular squaring simultaneously The proposed systolic array with less hardware complexity can be designed by making use of common-multiplicand multiplication in the right-to-left modular exponentiation over GF(2(m)). For the fast computation of the modular exponentiation, the proposed systolic array has 1.25 times improvement in area-time complexity when compared to existing multipliers. The proposed systolic array suffers a little loss in time complexity, but it has 1.44 times improvement in area complexity since it executes the common parts that exist in the simultaneous computation of both modular multiplication and squaring only once. It could be designed on VLSI hardware and used in IC cards. (C) 2001 Elsevier Science Ltd. All rights reserved.

关键词： public key cryptosystem montgomery algorithm common-multiplicand multiplication modular exponentiation systolic array

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VLSI design of RSA cryptosystem based on the Chinese remainder theorem

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JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 2001年第6期17卷 967-979页

作者： Wu, CH Hong, JH Wu, CW Natl Tsing Hua Univ Dept Elect Engn Hsinchu 300 Taiwan Da Yeh Univ Dept Elect Engn Changhua 515 Taiwan

This paper presents the design and implementation of a systolic RSA cryptosystem based on a modified montgomery's algorithm and the Chinese Remainder Theorem (CRT) technique, The CRT technique improves the throughput rate up to 4 times in the best case. The processing unit of the systolic array has 100% utilization because of the proposed block interleaving technique for multiplication and square operations in the modular exponentiation algorithm. For 512-bit inputs, the number of clock cycles needed for a modular exponentiation is about 0,13 to 0.24 million. The critical path delay is 6.13ns using a 0.6mum CMOS technology. With a 150 MHz clock, we can achieve an encryption/decryption rate of about 328 to 578 Kb/s.

关键词： cellular array montgomery algorithm modular multiplication Chinese remainder theorem (CRT) RSA public-key cryptography

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