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检索条件"主题词=Multi-/Many-core"

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Integrating multi-/many-cores in Avionics: Open Issues and Future Concepts 40

Integrating Multi-/Many-Cores in Avionics: Open Issues and F...

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IEEE/AIAA 40th Digital Avionics Systems Conference (DASC)

作者： Christmann, Anika Kostrzewa, Adam Ernst, Rolf Rockschies, Marius Halle, Martin Thielecke, Frank Peuker, Alexander Kuzolap, Alexander Steen, Meiko Hecker, Peter Nessitt, Kai-Frederik Saidi, Selma Tech Univ Carolo Wilhelmina Braunschweig Inst Comp & Network Engn Braunschweig Germany Hamburg Univ Technol Inst Aircraft Syst Engn Hamburg Germany Tech Univ Carolo Wilhelmina Braunschweig Inst Flight Guidance Braunschweig Germany TU Dortmund Univ Chair Embedded Syst Dortmund Germany

ISBN: (纸本)9781665434201

The demand on on-board computing power in the aerospace domain is increasing while multi-/many-core systems promise an overall performance enhancement. One of the main drivers is the accumulating set of functions in an avionic system, for example in the cockpit, flight navigation/guidance domain or image data processing. The upcoming obsolescence of single-core processors being replaced by multi-/many-core processors is addressed in recent research activities of the avionics community. Despite intensive research, there is still a lack of system design guidelines and experience how to transition existing applications from single- to multi-/many-core. This paper gives an overview on state-of-the-art methods, potential applications, and future concepts how to assess new avionics platform designs in a systematic way.

关键词： multi-/many-core safety-critical avionic systems

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Long Short-Term Memory Neural Network-based Power Forecasting of multi-core Processors

Long Short-Term Memory Neural Network-based Power Forecastin...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Sagi, Mark Rapp, Martin Khdr, Heba Zhang, Yizhe Fasfous, Nael Nguyen Anh Vu Doan Wild, Thomas Henkel, Joerg Herkersdorf, Andreas Tech Univ Munich TUM Chair Integrated Syst LIS Munich Germany Karlsruhe Inst Technol KIT Chair Embedded Syst CES Karlsruhe Germany

ISBN: (纸本)9783981926354

We propose a novel technique to forecast the power consumption of processor cores at run-time. Power consumption varies strongly with different running applications and within their execution phases. Accurately forecasting future power changes is highly relevant for proactive power/thermal management. While forecasting power is straightforward for known or periodic workloads, the challenge for general unknown workloads at different voltage/frequency (v/f)-levels is still unsolved. Our technique is based on a long short-term memory (LSTM) recurrent neural network (RNN) to forecast the average power consumption for both the next 1 ms and 10 ms periods. The runtime inputs for the LSTM RNN are current and past power information as well as performance counter readings. An LSTM RNN enables this forecasting due to its ability to preserve the history of power and performance counters. Our LSTM RNN needs to be trained only once at design-time while adapting during run-time to different system behavior through its internal memory. We demonstrate that our approach accurately forecasts power for unseen applications at different v/f-levels. The experimental results shows that the forecasts of our LSTM RNN provide 43% lower worst case error for the 1ms forecasts and 38% for the 10ms forecasts, compared to the state of the art.

关键词： Power Forecasting Recurrent Neural Network multi-/many-core

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Optimized All-to-all Connection Establishment for High-Performance MPI Libraries over InfiniBand 30

Optimized All-to-all Connection Establishment for High-Perfo...

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30th International Conference on High Performance Computing, Data, and Analytics (HiPC)

作者： Xu, Shulei Kuncham, Goutham Kalikrishna Reddy Abduljabbar, Mustafa Subramoni, Hari Panda, Dhabaleswar K. (Dk) Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA

ISBN: (纸本)9798350383225

In modern multi-/many-core HPC systems, the increasing number of processor cores presents new challenges in managing parallel compute workloads across multiple nodes. One crucial aspect that significantly impacts the startup phase of parallel MPI jobs is the methodology used for connection establishment. In this paper, we investigate the limitations of existing all-to-all connection establishment designs in-depth, identify the primary sources of performance overhead, and propose an optimized all-to-all connection establishment design. This is done through an enforced ordering rank-by-rank scheme that significantly cuts down on the data exchange overhead via PMI. To address the increasing overheads associated with queue pair creation and synchronization, we explore multi-thread parallelism and incorporate CPU affinity awareness into our design. We implement our proposed design in the state-of-the-art MVAPICH2 MPI library and conduct extensive experiments on two emerging architectures. Through a comprehensive performance evaluation of these architectures, we demonstrate the efficacy of our optimized all-to-all connection establishment design. Our microbenchmark results reveal up to 20 times faster MPI Init time, while evaluations with application kernels exhibit a 31% improvement in throughput.

关键词： multi-/many-core HPC MPI Job Startup Connection Establishment InfiniBand RDMA

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Heuristic Contention-Free Scheduling Algorithm for multi-core Processor using LET Model 24

Heuristic Contention-Free Scheduling Algorithm for Multi-cor...

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IEEE/ACM 24th International Symposium on Distributed Simulation and Real Time Applications (DS-RT)

作者： Igarashi, Shingo Ishigooka, Tasuku Horiguchi, Tatsuya Koike, Ryotaro Azumi, Takuya Saitama Univ Grad Sch Sci & Engn Saitama Japan Hitachi Ltd Ctr Technol Innovat Controls Res & Dev Grp Tokyo Japan

ISBN: (纸本)9781728173436

Embedded systems, e.g., self-driving systems and advanced driver-assistance systems (ADAS), require computing platforms with high computing power and low power consumption. multi-/many-core platforms satisfy these requirements effectively. However, for hard real-time applications, multiple demands on shared resources can impede real-time performance, and memory is one resource that can impair the desired performance significantly. Therefore, it is important that memory access timing be deterministic to facilitate predictability. To realize this, the Logical Execution Time (LET) paradigm is currently attracting attention. This paper proposes a theoretical scheduling method for a model applying the LET paradigm to directed acyclic graph (DAG) nodes for a multi-/many-core platform. The proposed method considers communication timing between nodes and generates a schedule that does not cause communication contentions. In addition, the proposed method attempts to distribute tasks and reduce LET intervals to address increased execution times due to the implementation of the LET paradigm. In the evaluation, we observed that the proposed method improved the schedule length by up to 40%.

关键词： multi-rate DAG multi-/many-core communication contention list-scheduling logical execution time

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Heuristic contention-free scheduling algorithm for multi-core processor using LET model 20

Heuristic contention-free scheduling algorithm for multi-cor...

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Proceedings of the IEEE/ACM 24th International Symposium on Distributed Simulation and Real Time Applications

作者： Shingo Igarashi Tasuku Ishigooka Tatsuya Horiguchi Ryotaro Koike Takuya Azumi Saitama University Hitachi Ltd.

关键词： communication contention multi-/many-core multi-rate DAG list-scheduling logical execution time

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Contention-Free Scheduling Algorithm Using LET Paradigm for Clustered many-core Processor 25

Contention-Free Scheduling Algorithm Using LET Paradigm for ...

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25th IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications (DS-RT)

作者： Yano, Atsushi Igarashi, Shingo Azumi, Takuya Saitama Univ Grad Sch Sci & Engn Saitama Japan

ISBN: (纸本)9781665433266

Self-driving systems require multi-/many-core platforms with high computing power and low power consumption. However, for hard real-time applications, multiple demands on shared resources can impede real-time performance. Therefore, making the timing of memory access deterministic is important. The logical execution time (LET) paradigm has gained attention as a means to achieve this purpose. However, this approach lacks scalability owing to the overhead caused because the LET paradigm is set longer than the actual execution time of the task. This paper proposes a theoretical scheduling method for a model applying the LET paradigm to the directed acyclic graph (DAG) nodes for a multi-/many-core platform. The proposed method considers communication timing and generates a schedule that does not cause communication contentions. In addition, the proposed method performs a parallel calculation of tasks to deal with the overhead caused by adopting the LET paradigm.

关键词： multi-rate DAG multi-/many-core communication contention list-scheduling logical execution time

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Contention-free scheduling algorithm using LET paradigm for clustered many-core processor 21

Contention-free scheduling algorithm using LET paradigm for ...

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Proceedings of the 2021 IEEE/ACM 25th International Symposium on Distributed Simulation and Real Time Applications

作者： Atsushi Yano Shingo Igarashi Takuya Azumi Saitama University

ISBN: (纸本)9781665433266

关键词： multi-rate DAG communication contention logical execution time list-scheduling multi-/many-core

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Machine-agnostic and Communication-aware Designs for MPI on Emerging Architectures 34

Machine-agnostic and Communication-aware Designs for MPI on ...

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34th IEEE International Parallel and Distributed Processing Symposium (IPDPS)

作者： Hashmi, Jahanzeb Maqbool Xu, Shulei Ramesh, Bharath Bayatpour, Mohammadreza Subramoni, Hari Panda, Dhabaleswar K. (DK) Ohio State Univ Columbus OH 43210 USA

ISBN: (数字)9781728168760

ISBN: (纸本)9781728168760

Modern multi-/many-cores offer higher core-density, hardware multi-threading, deeper memory hierarchies, and diverse architectural capabilities. While emerging cloud-based HPC systems are able to deliver near-native performance, they bring more diversity to the architectures. The Message Passing Interface (MPI) offers the flexibility to arbitrarily bind application processes to CPU cores, however the static nature of these binding policies typically does not take applications' communication patterns and underlying machine architecture into consideration. This lack of association between the dynamic nature of applications and architectural diversity offered by modern processors makes it difficult for the application developers and MPI designers to exploit modern multi-/many-core systems to their full potential. In this paper, we propose a set of low-level benchmarking based approaches and MPI-level designs to infer vendor-specific machine characteristics e.g., physical to virtual machine topologies, and dynamic communication patterns of the applications. By utilizing this information, we propose two novel algorithms to construct efficient MPI mappings for any given architecture and application communication pattern. The proposed designs are implemented in the MVAPICH2 MPI library and are evaluated on three different architectures using various micro-benchmarks and application kernels. We demonstrate up to 2X performance improvement for MPI collectives, and up to 3.5X and 26% improvement for NAS-CG and miniAMR application kernels, respectively.

关键词： multi-/many-core SMP MPI HPC Azure Cloud Process Placement Communication Graphs Topology

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Mapping Method of MATLAB/Simulink Model for Embedded many-core Platform 28

Mapping Method of MATLAB/Simulink Model for Embedded Many-Co...

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28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)

作者： Honda, Kentaro Kojima, Sasuga Fujimoto, Hiroshi Edahiro, Masato Azumi, Takuya Saitama Univ Grad Sch Sci & Engn Saitama Japan Osaka Univ Grad Sch Engn Sci Suita Osaka Japan Technol Headquarters eSOL Co Ltd Tokyo Japan Nagoya Univ Grad Sch Informat Nagoya Aichi Japan

ISBN: (纸本)9781728165820

multi-/many-core processors are being increasingly used to reduce power consumption and improve performance. In addition, the use of Model-Based Development for embedded systems has been increasing. Relative to these trends, Model-Based Parallelizer (MBP) has an essential role in parallelizing applications (i e, Simulink blocks) at the model level. MBP maps Simulink blocks to cores using various types of information such as block characteristics, a C code, and the multi-/many-core hardware implementation. However, MBP does not consider many-core hardware with cluster structures. This paper proposes an algorithm that decides on core allocations by considering cluster structures. The proposed algorithm combines two other algorithms: one algorithm uses the core allocation of MBP and path analysis at the clusterlevel and considers the influence of communication contention to decide on cluster allocations, and the other algorithm uses the results of MBP and remaps cluster allocations. The proposed algorithm produces better results than its component algorithms could separately. Evaluations demonstrate that the proposed algorithm obtained the better results than the existing method in terms of execution time on random and real models.

关键词： Embedded Systems Model-Based Development multi-/many-core

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Designing Efficient Shared Address Space Reduction Collectives for multi-/many-cores 32

Designing Efficient Shared Address Space Reduction Collectiv...

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27th International Heterogeneity in Computing Workshop in conjunction with 32nd IEEE International Parallel and Distributed Processing Symposium (IPDPS)

作者： Hashmi, Jahanzeb Maqbool Chakraborty, Sourav Bayatpour, Mohammadreza Subramoni, Hari Panda, Dhabaleswar K. (DK) Ohio State Univ Columbus OH 43210 USA

ISBN: (纸本)9781538643686

State-of-the-art designs for the hierarchical reduction collective operation in MPI that work on the concept of distributed address spaces incur the cost of intermediate copies inside the MPI library to stage the data between processes. Such additional copies can severely affect the performance especially on emerging many-core architectures like Intel Xeon/Xeon Phi and OpenPOWER. In this paper, we take up this challenge and study the trade-offs involved in designing high-performance and scalable, "shared address space"-based communication primitives on top of XPMEM using basic point-to-point primitives in MPI. We then redesign the reduction collective operations using the knowledge gained from the initial studies. Our proposed designs at the collective level enable a process to offload communication and computation operations to intra-node peers without the need for additional intermediate copies resulting in a truly "zerocopy" design for MPI Reduce and MPI Allreduce. We further develop a theoretical model to analytically study the impact such designs can have on the performance of collective communication primitives. We evaluate the proposed designs with microbench-marks, HPC, and Deep Learning applications on three different multi-/many-core architectures (Broadwell, Knights Landing, and OpenPOWER). The proposed designs show up to 3x improvement in latency of Reduce and Allreduce benchmarks, up to 37% improvement in the runtime of MiniAMR, and up to 19% reduction in the training time of AlexNet deep neural network compared to existing state-of-the-art MPI libraries. To the best of our knowledge, this is the first research work that studies the impact of XPMEM based shared address space designs on the performance of collective operations in a distributed memory programming model like MPI at scale.

关键词： Collective Communication Shared Address Space Kernel-assisted XPMEM multi-/many-core MPI HPC

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