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IEEE 73rd Electronic Components and Technology Conference (ECTC)

作者： Yip, Laurene Tsai, James Lin, Rosa Hsu, Ian MediaTek Inc San Jose CA 95134 USA MediaTek Inc Hsinchu Taiwan

ISBN: (纸本)9798350334982

2.5D silicon interposer packages have been widely adopted for high-end applications such as datacenter, networking, and artificial intelligence. To meet the increasing demand for higher performance and greater bandwidth, the die and package sizes have been increasing due to the need for higher levels of device integration. As the package size increases, chip-to-package interaction (CPI) will become more challenging to manage. The main challenges with large 2.5 devices are warpage, C4 bump integrity, underfill cracking, and mold compound delamination caused by interposer corner stress. In our study, package warpage and reliability of a chip-on-wafer-on-substrate (CoWoS) multi-chip module (MCM) package with two 1.5X reticle interposers and a package size of 85mmX85 mm were investigated. The coefficient of thermal expansion (CTE) mismatch between different package materials can cause warpage and induce mechanical stresses that can lead to bump cracks, underfill delamination/cracking, and other failures in the package. We will discuss package design methods to reduce interposer die stress to enhance package reliability. By using finite element stress analysis to optimize the device layout, C4 bump standoff height, and interposer structure, large size 2.5D MCM packages were developed and evaluated with reliability testing.

关键词： 2.5D multi-chip module interposer package warpage CoWoS reliability

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Temperature-Aware Sizing of multi-chip module Accelerators for multi-DNN Workloads

Temperature-Aware Sizing of Multi-Chip Module Accelerators f...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Shukla, Prachi Aguren, Derrick Burd, Tom Coskun, Ayse K. Kalamatianos, John Boston Univ Boston MA 02215 USA Adv Micro Devices Inc Santa Clara CA 95054 USA

ISBN: (纸本)9798350396249

This paper demonstrates the need for temperature awareness in sizing accelerators to target multi-DNN workloads. To that end, we build TESA, a TEmperature-aware methodology that Sizes and places Accelerators to balance both the cost and power of a multi-chip module (MCM), including DRAM power for multi-deep neural network workloads. TESA tunes the accelerator chiplet size and inter-chiplet spacing to generate a temperature-aware MCM layout, subject to user-defined latency, area, power, and thermal constraints. Using TESA for both 2D and 3D systolic array-based chiplets, we demonstrate up to 44% MCM cost savings and 63% DRAM power savings, respectively, over a temperature-unaware baseline at iso-frequency and iso-interposer area. We also demonstrate a need for TESA to obtain feasible MCM configurations for multi-DNN workloads such as augmented/virtual reality (AR/VR).

关键词： 3D stacking thermal awareness multi-DNN workloads systolic arrays multi-chip module

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Thermal-Aware SoC Macro Placement and multi-chip module Design Optimization with Bayesian Optimization 73

Thermal-Aware SoC Macro Placement and Multi-chip Module Desi...

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IEEE 73rd Electronic Components and Technology Conference (ECTC)

作者： Molter, Michael Kumar, Rahul Koller, Sonja Bhatti, Osama Waqar Ambasana, Nikita Rosenbaum, Elyse Swaminathan, Madhavan Univ Illinois Urbana IL 61801 USA Penn State Univ University Pk PA 16802 USA Intel Deutschland GmbH Neubiberg Germany Georgia Inst Technol Atlanta GA 30332 USA Intel India DCAI DPE Chennai Tamil Nadu India

ISBN: (纸本)9798350334982

The effect of temperature on the reliability and performance of electrical components and integrated circuits warrants the inclusion of thermal considerations in the early stages of electronic system design. However, the many design parameters involved in the design of the package and the die or macro placement, along with the use of expensive thermal simulations, poses difficulty for conventional optimization algorithms. To overcome that hurdle, this work proposes an efficient Bayesian optimization algorithm which is demonstrated for two early-stage design problems. First, the proposed algorithm is used for the thermal-aware placement of macros with a variable aspect ratio. Second, the proposed Bayesian optimization algorithm is utilized in a two-stage process to optimize the die placement and the package design parameters of a multi-chip module.

关键词： Bayesian optimization Macro Placement Floor-planning Die placement multi-chip module

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EXPERIMENTAL AND NUMERICAL INVESTIGATION OF SINGLE-PHASE LIQUID COOLING FOR HETEROGENEOUS INTEGRATION multi-chip module

EXPERIMENTAL AND NUMERICAL INVESTIGATION OF SINGLE-PHASE LIQ...

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ASME International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems (InterPACK)

作者： Gharaibeh, Ahmad R. Soud, Qusai Manaserh, Yaman Tradat, Mohammed Sammakia, Bahgat SUNY Binghamton Binghamton NY 13902 USA

ISBN: (纸本)9780791887516

The variety of new electronic packaging technologies has grown significantly over the last 20 years as a result of market demands for higher device performance at lower costs and in less space. Those demands have pushed for heterogeneous packaging, where computer chips with different stack heights are closely packed, creating non-uniform multicore chip heat flux and temperature and additional challenges for thermal management. Without implementing an appropriate thermal management strategy for heterogeneous packages, large temperature gradients can be observed within the package, which would increase the thermal stresses on the chip and raise reliability issues. Therefore, removing excessive heat flux will improve the reliability and efficiency of those electronic components. The development of high-heat flux applications is straining the capabilities of air-cooling systems, which are nearing their limitations. Single-phase liquid cooling methods have proven to be reliable, usable, and energy-efficient methods for cooling high-heat flux devices. With the introduction of packages with multiple-chip modules (MCMs), the cold plates of future generations are expected to handle multiple hot spots at the same time. To enable the effective removal of heat from the chips, special cold plate designs for each type of package are required. Many methods may be used to improve thermohydraulic performance, including the use of improved fin designs, flow restriction to breakdown the boundary layer, and the integration of mixing mechanisms to improve the mixing between the fluid and channel walls. To mimic this real-life scenario of such packaging in high-heat flux applications, an experimental setup was designed and built. The design of the new experimental setup consists of four identical 1.2 cm x 1.2 cm ceramic heaters, each of which is connected to a separate power supply and can reach a heat flux of 140 W/cm(2). Accordingly, this mock package is capable of delivering different

关键词： multi-chip module Liquid cooling Heat sink Data centers Heat transfer

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Constructal design for the layout of multi-chip module based on thermal-flow-stress coupling calculation

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MICROELECTRONICS RELIABILITY 2021年 127卷 114417-114417页

作者： Nan, Gang Xie, Zhihui Guan, Xiaonan Ji, Xiangkun Lin, Daoguang Naval Univ Engn Coll Power Engn Wuhan 430033 Peoples R China Naval Univ Engn Teaching Sect Math Dept Basic Courses Wuhan 430033 Peoples R China Hunan Univ Humanities Sci & Technol Sch Energy & Electromech Engn Loudi 417000 Peoples R China

The thermal-flow-stress coupling model of multi-chip module with uniform heat generation under natural convection condition is established. Taking the chip aspect ratio and edge distance as design variables, a comprehensive performance indicator considering the maximum temperature, maximum thermal stress and maximum deformation is constructed to optimize the layout of chips with the constraints of the total occupied areas of printed circuit board and chips according to constructal theory. The results show that the comprehensive performance indicator decreases monotonically with the increase of the chip aspect ratio under the constraints of equal spacing, hence the chips should be designed as thin as possible according to the design requirements. Releasing the constraint of equal spacing, the comprehensive performance indicator increases monotonically with the increase of the edge distance when the chip aspect ratio is constant;the comprehensive performance indicator first decreases and then increases with the increase of chip aspect ratio when the edge distance is constant. The comprehensive performance indicator of the multi-chip module can be reduced by 0.65, the maximum temperature, the maximum thermal stress and the maximum deformation can be reduced by 6.28%, 9.44% and 9.66%, respectively. The methods and results herein could provide theoretical guidance for the thermal design of layout of multi-chip module.

关键词： Constructal theory multi-chip module Natural convection Thermal design multi-physics field coupling Thermal reliability

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Design Considerations for multi-chip module Silicon Photonic Transceivers 3

Design Considerations for Multi-Chip Module Silicon Photonic...

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Conference on Metro and Data Center Optical Networks and Short-Reach Links III

作者： Abrams, Nathan C. Cheng, Qixiang Glick, Madeleine Manzhosov, Evgeny Jezzini, Moises Morrissey, Padraic O'Brien, Peter Bergman, Keren Columbia Univ Dept Elect Engn Lightwave Res Laboraotry New York NY 10027 USA Tyndall Natl Inst Cork Ireland

ISBN: (纸本)9781510633803

High bandwidth density silicon photonic interconnects offer the potential to address the massive increase in bandwidth demands for data center traffic and high performance computing. One of the major challenges in realizing silicon photonics transceivers is the integration and packing of photonic ICs (PIC) with electronic ICs (EIC). This paper presents our version one, 2.5D integrated multi-chip module (MCM) transceiver for 4 channel wavelength division multiplexing (WDM) operation, targeting 10 Gbps per channel. We identify five key areas critical to successful integration of MCM transceivers, which we have used in developing our version two MCM transceiver: integration architecture, equivalent circuit model development, PIC to EIC interface modelling, MCM I/O design, and design for assembly.

关键词： Silicon Photonics multi-chip module Interposer 2.5D Integration Optical Interconnects Wavelength Division multiplexing

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Silicon Photonic multi-chip module Interconnects for Disaggregated Data Centers 24

Silicon Photonic Multi-Chip Module Interconnects for Disaggr...

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International Conference on Optical Network Design and Modeling (ONDM)

作者： Abrams, Nathan C. Glick, Madeleine Bergman, Keren Columbia Univ Dept Elect Engn New York NY 10027 USA

ISBN: (纸本)9783903176218

We present our development of 2.5D integrated multi chip module silicon photonic transceivers for disaggregated applications, such as big data and machine learning algorithms. Disaggregation of data center resources to improve application efficiency and performance can be achieved through photonic switching networks. Our four-channel transceiver provides the electro-optic interface between electrical data generation and photonic switching to enable disaggregation within data centers.

关键词： Silicon Photonics multi-chip module Interposer 2.5D Integration Optical Interconnects Disaggregation

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Research of Reconstructed Wafer Surface Planarity on the Metall-Compound-Silicon Boundary for multi-chip module with Embedded Dies

Research of Reconstructed Wafer Surface Planarity on the Met...

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IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)

作者： Pogudkin, Anton V. Belyakov, Igor A. Vertyanov, Denis V. Kruchinin, Sergei M. Timoshenkov, Sergei P. Natl Res Univ Elect Technol MIET Inst Nano & Microsyst Technol Moscow Russia

ISBN: (纸本)9781728103396

One of the most important problem for multi-chip module manufacturing technology with embedded in carrier cavities dies is ensuring surface planarity. Critical areas in this case are the gaps between the carrier and dies, filled with compound. Absence of planar surface in these areas can lead to defects in commutation layers, internal stresses and, as result, to significant decrease in assembly reliability. In this article, surface reliefs of carrier with embedded dies after molding with variety epoxy and silicone based polymers have been investigated. As a result, the minimum irregularity height of about 4 microns was achieved for optimal combination of molding compound and polyimide coating in the minimum gap with of about 250 microns.

关键词： embedded die multi-chip module surface planarity molding compound

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Analysis and Solution of Glass Cracking of Low Frequency Connector in multi-chip module 20

Analysis and Solution of Glass Cracking of Low Frequency Con...

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20th International Conference on Electronic Packaging Technology (ICEPT)

作者： Jin, J. F. Ren, R. Gou, H. Z. 38th Res Inst CETC Hefei Peoples R China Guizhou Space Appliance Co Ltd Guiyang Peoples R China

ISBN: (纸本)9781728150642

multi-chip modules contain a large number of bare chips, which are sensitive to moisture in the packaging atmosphere. In order to ensure the long-term reliability of this kind of modules, it is necessary to seal the module package. Low-frequency connector is an indispensable part of multi-chip module, which is used to transmit internal and external electrical signals of modules. During the screening test, the phenomenon of unqualified hermeticity of some sealed modules appeared. modules exhibit a leak rate greater than 1.0x10(-3) Pa.m(3)/s during the tracer gas helium (He) fine leak test. Further inspection of the low-frequency connector body reveals that there are slender cracks in the connector glass body. The analysis shows that the reason of glass cracking is the thermal stress level of the module during welding heating exceeds the tensile strength of the glass, which leads to failure. Temperature difference exists in different positions of the connector during laser welding of cover plate, and cannot be eliminated by welding process optimization. After eliminating the internal defects of the glass body, the problem of glass body cracking did not occur in the process of multi-round step-by-step screening test, and the sealing test of module products was qualified after each test.

关键词： multi-chip module low frequency connector glass cracking experimental design

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Simba: Scaling Deep-Learning Inference with multi-chip-module-Based Architecture 52

Simba: Scaling Deep-Learning Inference with Multi-Chip-Modul...

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52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Shao, Yakun Sophia Clemons, Jason Venkatesan, Rangharajan Zimmer, Brian Fojtik, Matthew Jiang, Nan Keller, Ben Klinefelter, Alicia Pinckney, Nathaniel Raina, Priyanka Tell, Stephen G. Zhang, Yanqing Dally, William J. Emer, Joel Gray, C. Thomas Khailany, Brucek Keckler, Stephen W. NVIDIA Santa Clara CA 95051 USA

ISBN: (纸本)9781450369381

Package-level integration using multi-chip-modules (MCMs) is a promising approach for building large-scale systems. Compared to a large monolithic die, an MCM combines many smaller chiplets into a larger system, substantially reducing fabrication and design costs. Current MCMs typically only contain a handful of coarse-grained large chiplets due to the high area, performance, and energy overheads associated with inter-chiplet communication. This work investigates and quantifies the costs and benefits of using MCMs with fine-grained chiplets for deep learning inference, an application area with large compute and on-chip storage requirements. To evaluate the approach, we architected, implemented, fabricated, and tested Simba, a 36-chiplet prototype MCM system for deep-learning inference. Each chiplet achieves 4 TOPS peak performance, and the 36-chiplet MCM package achieves up to 128 TOPS and up to 6.1 TOPS/W. The MCM is configurable to support a flexible mapping of DNN layers to the distributed compute and storage units. To mitigate inter-chiplet communication overheads, we introduce three tiling optimizations that improve data locality. These optimizations achieve up to 16% speedup compared to the baseline layer mapping. Our evaluation shows that Simba can process 1988 images/s running ResNet-50 with batch size of one, delivering inference latency of 0.50 ms.

关键词： multi-chip module neural networks accelerator architecture

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