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17th IEEE International Conference on Industrial Informatics (INDIN)

作者： Ramakrishnan, Bharath Tradat, Mohammad Hadad, Yaser Ghose, Kanad Sammakia, Bahgat SUNY Binghamton Dept Mech Engn Binghamton NY 13902 USA SUNY Binghamton Dept Comp Sci Binghamton NY USA

ISBN: (纸本)9781728129273

Miniaturization of microelectronic components comes at a price of high heat flux density. By adopting liquid cooling, the rising demand of high heat flux devices can be met while the reliability of the microelectronic devices can also be improved to a greater extent. Liquid cooled cold plates are largely replacing air based heat sinks for electronics in data center applications, thanks to its large heat carrying capacity. A bench level study was carried out to characterize the thermohydraulic performance of microchannel cold plates which uses warm De-Ionized (DI) water for cooling multi chip modules (MCM). A laboratory built mock package housing mock chips and a heat spreader was employed while assessing the thermal performance of three different cold plate designs at varying coolant flow rate and temperature. The case temperature measured at the heat spreader for varying flow rates and input power were essential in identifying the convective resistance corresponding to the cold plates. The flow performance was evaluated by the measuring the pressure drop across cold plate module at varying flow rates. Cold plate with the enhanced microchannel design yielded better results compared to a traditional parallel microchannel design. The experimental results were validated using a numerical model which is further optimized for improved geometric designs. Finally, an estimation of chiller operating cost was obtained for a 100% air cooled facility and compared their performance to that of a 60% warm water cooled facility.

关键词： cold plates microchannels multi-chip module data centers chiller

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Investigation of the warpage modeling technique for thick multi-chip module encapsulated by compression molding

Investigation of the warpage modeling technique for thick mu...

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International Conference on Electronics Packaging (ICEP)

作者： Suzuki, Kosuke Sanada, Yuki Uchibori, Shinya Kashiwazaki, Atsushi Imada, Masaji DENSO CORP Semicond Packaging R&D Div 1-1 Showa Cho Kariya Aichi Japan

ISBN: (纸本)9784990218836

It is an important issue to estimate and control the warpage of the semiconductor package for the reliability and the heat dissipation of the contact with the circuit board and the case. Especially, in a multi-chip module (MCM), which encapsulate several electronic components, the increased size of the package expands the amount of the warpage although the curvature is same as that of a single chip. For general encapsulated packages, the cure shrinkage of the mold resin and the mismatch of a coefficient of thermal expansion (CTE) are the factor of the warpage. We have studied the package structure encapsulated by compression molding that can encapsulate large area size with lager number of packages. Also, compression molding technology enables the different thickness packages to be encapsulated with a common molding die. In this study, we examined the warpage of a thick-mold-resin module formed on a printed circuit board (PCB), and found that the direction of the warpage was opposite to the estimation based on the uniform cure shrinkage of the mold resin. To understand the mechanism of this warpage behavior, we focused on the non-uniform distribution of the temperature inside a thick-mold-resin module under compression molding, and confirmed that the curing degrees are not uniform along the thickness of the mold resin. Then, we modeled the distribution of the cure shrinkage along the thickness, and estimated the warpage using finite element method (FEM) analysis. The result of the FEM was consistent with the direction of the measured warpage. We established the modeling technique to estimate the warpage of the thick-mold-resin module encapsulated by compression molding.

关键词： compression molding warpage cure shrinkage multi-chip module semiconductor package printed circuit board

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multi-chip module (MCM-D) Using Thin Film Technology 29

Multi-Chip Module (MCM-D) Using Thin Film Technology

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29th Symposium on Microelectronics Technology and Devices (SBMicro)

作者： Adamo, Cristina B. Flacker, Alexander Freitas, Wilson Teixeira, Ricardo C. da Silva, Michele O. Rotondaro, Antonio L. P. Renato Archer Ctr Informat Technol Campinas SP Brazil

ISBN: (纸本)9781479946969

This work presents results of the multi-chip module-Deposited technology built with thin film processes over a substrate of alumina and oxidized silicon that was used to micro-fabricate passive components (capacitors, resistors, inductors). Metal layers were deposited by sputtering, electrolytic and electroless techniques and benzocyclobutene was used as dielectric. Electrical characteristics of passive components and filters were evaluated indicating that the testchip and processes were effective to manufacture the devices.

关键词： multi-chip module passive components benzocyclobutene thin film deposition

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Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor chips and multi-chip module

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2014年第1期49卷 9-18页

作者： Warnock, James Chan, Yuen Harrer, Hubert Carey, Sean Salem, Gerard Malone, Doug Puri, Ruchir Zitz, Jeffrey A. Jatkowski, Adam Strevig, Gerald Datta, Ayan Gattiker, Anne Bansal, Aditya Mayer, Guenter Chan, Yiu-Hing Mayo, Mark Rude, David L. Sigal, Leon Strach, Thomas Smith, Howard H. Wen, Huajun Mak, Pak-kin Shum, C. -L. Kevin Plass, Donald Webb, Charles IBM Syst & Technol Grp Yorktown Hts NY 10598 USA IBM Syst & Technol Grp Poughkeepsie NY 12601 USA IBM Syst & Technol Grp D-71032 Boblingen Germany IBM Syst & Technol Grp Williston VT 05495 USA IBM Res Yorktown Hts NY 10598 USA IBM Syst & Technol Grp Hopewell Jct NY USA IBM Syst & Technol Grp Austin TX 78758 USA IBM Syst & Technol Grp Bangalore 560071 Karnataka India IBM Res Austin TX 78758 USA

This work describes the circuit and physical design implementation of the processor chip (CP), level-4 cache chip (SC), and the multi-chip module at the heart of the EC12 system. The chips were implemented in IBM's high-performance 32nm high-k/metal-gate SOI technology. The CP chip contains 6 super-scalar, out-of-order processor cores, running at 5.5 GHz, while the SC chip contains 192 MB of eDRAM cache. Six CP chips and two SC chips are mounted on a high-performance glass-ceramic substrate, which provides high-bandwidth, low-latency interconnections. Various aspects of the design are explored in detail, with most of the focus on the CP chip, including the circuit design implementation, clocking, thermal modeling, reliability, frequency tuning, and comparison to the previous design in 45nm technology.

关键词： chip integration chip thermal modeling circuit design methodology clock distribution clock grid CMOS digital integrated circuits design for reliability design for test digital circuits EC12 high-frequency CMOS design high-k/metal-gate microprocessor test microprocessors multi-chip module NBTI PBTI power efficiency reliability SRAM structured synthesis system z 32 nm SOI VLSI design ZEC12 zEnterprise

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Terabit direct-detection optical engines and switching circuits in multi-chip modules for Data-center networks and the 5G optical fronthaul

Terabit direct-detection optical engines and switching circu...

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Italian Conference on Optics and Photonics (ICOP)

作者： Andrianopoulos, Efstathios Massaouti, Maria Groumas, Panos Piat, Anna Chiado Pagano, Annachiara Verbeke, Marijn Kouloumentas, Christos Dekker, Ronald Tegegne, Zerihun Kresse, Martin Bakopoulos, Paraskevas Avramopoulos, Hercules Natl Tech Univ Athens Sch Elect & Comp Engn Athens Greece Optagon Photon Athens Greece Telecom Italia Ip & Transport Innovat Turin Italy Telecom Italia Access Innovat Turin Italy Univ Ghent Dept Informat Technol Imec IDLab Ghent Belgium LioniX Int BV Enschede Netherlands PHIX Photon Assembly Enschede Netherlands Fraunhofer HHI Berlin Germany NVIDIA Ermou 56 Athens 10563 Greece

Terabit capacity optical engines for data center and access networks are gaining momentum supported by a pool of technological innovations that are promising low cost and simple design for a wide range of application ... 详细信息

ISBN: (数字)9781665488815

ISBN: (纸本)9781665488815

关键词： optical transceivers data centers integrated photonics multi-chip module SDM multi core fiber O band

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Thermal challenges in heterogeneous packaging: Experimental and machine learning approaches to liquid cooling

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APPLIED THERMAL ENGINEERING 2025年 260卷

作者： Gharaibeh, Ahmad R. Rangarajan, Srikanth Soud, Qusai Al-Zubi, Omar Manaserh, Yaman Sammakia, Bahgat SUNY Binghamton Ctr ES2 Dept Mech Engn New York NY 13902 USA SUNY Binghamton Dept Syst Sci & Ind Engn New York NY USA

In recent years, electronic packaging has evolved significantly to meet demands for higher performance, lower costs, and smaller designs. This shift has led to heterogeneous packaging, which integrates chips of varying stack heights and results in non-uniform heat flux and temperature distributions. These conditions pose substantial thermal management challenges, as they can create large temperature gradients, which increase thermal stress and potentially compromise chip reliability. This study explores single-phase liquid cooling for multi-chip modules (MCMs) through a comprehensive experimental and machine learning approach. It investigates the impact of chip spacing, height, fluid flow rate, fluid inlet location, and heat flux uniformity on chip temperature and the thermohydraulic performance of a commercial cold plate. Results show that increasing coolant flow from 1 LPM to 2 LPM decreased thermal resistance by 26 %, with heat losses remaining below 5 %. The left inlet configuration improved temperature uniformity compared to the right, though both yielded comparable thermal performance. Adjusting heater spacing impacted temperature distribution based on inlet position, and lowering one heater by 1 mm raised its temperatures by 15 degrees C due to increased thermal resistance from thermal interface material. A transient test demonstrated the cold plate's quick response to power surges, in which there is only a 1 degrees C spike above steady state. Complementing these findings, an Artificial Neural Network (ANN) model was developed with optimized architecture specifically for the unique challenges of this study. The ANN model was rigorously validated using an independent dataset, achieving highly accurate temperature predictions (R2 = 0.99) within 2.5 % of experimental values, which demonstrates this framework's potential for optimizing MCM thermal performance.

关键词： multi-chip module Liquid cooling Machine learning Neural network Heat sink Data centers Heat transfer Thermal management

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High Power Thermal Test Vehicle with 2-Phase Cooling for AI Datacenters, 5G RAN, and EDGE Compute Nodes 74

High Power Thermal Test Vehicle with 2-Phase Cooling for AI ...

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IEEE 74th Electronic Components and Technology Conference (ECTC)

作者： Liu, Yang Basavanhally, Nagesh Earnshaw, Mark Salamon, Todd Papazian, Rick Hu, Ting-Chen Cappuzzo, Mark Kopf, Rose Apigo, David Farah, Bob Faisal, Syed Roy, Rishav Nokia Bell Labs Murray Hill NJ 07974 USA

ISBN: (纸本)9798350375985;9798350375992

In this paper, we introduce the design and fabrication of a high-power thermal test vehicle (TTV) equipped with a two-phase cooling system, targeting improved thermal management in multi-chip modules (MCMs) for AI datacenters, 5G RAN, and EDGE compute nodes. With the rise in device integration and component power densities, conventional cooling methods fall short, prompting the need for innovative approaches to achieve efficient heat dissipation. The TTV utilizes advanced heterogeneous integration techniques on a low-temperature cofired ceramic (LTCC) substrate, designed to reliably dissipate over 1000 W of heat. This provides a robust platform for testing advanced two-phase cooling strategies to effectively remove heat from densely packed silicon dies, thus addressing the thermal challenges inherent in modern electronics. We elaborate on the fabrication of two variations of the TTV: the first comprising six X1 MCM modules, each measuring 25 mm x 38 mm, and the second a single X6 module measuring 76 mm x 76 mm, showcasing the robustness of the process. These TTVs are engineered to manage power dissipation of up to 1008 W, with logic chips experiencing background power densities of approximately 34 W/cm<^>2 and hotspots peaking at 400W/cm<^>2, while HBM stack chips exhibit a heat flux of 16 W/cm<^>2. The logic chips, measuring 20 mm x 20 mm, and the HBM stacks, measuring 10 mm x 10 mm, closely replicate the specifications of cutting-edge AI hardware. The importance of this work lies in its capacity to offer a scalable and dependable testing platform for advanced thermal management strategies in high-performance computing. By leveraging two-phase cooling, it paves the way toward more reliable and efficient computing infrastructures, effectively addressing the challenges posed by high power and heat flux in contemporary electronic devices.

关键词： MCM multi-chip module two-phase cooling OHP Thermal Test Vehicle TTV

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Disintegrating Manycores: Which Applications Lose and Why? 16

Disintegrating Manycores: Which Applications Lose and Why?

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16th International Workshop on Network on chip Architectures (NoCArc)

作者： Brkic, Isidor R. Jeffrey, Mark C. Univ Toronto Toronto ON Canada

ISBN: (纸本)9798400703072

The economics of Moore's Law are stumbling, so vendors of many-core architectures are transitioning from single-die monolithic designs to multi-chiplet disintegrated systems within a package. Disintegration lowers cost for the same number of cores but bottlenecks the interconnect. Ideally, disintegration should increase performance per dollar: cost savings should outweigh the disintegration slowdown. Although industry has reported cost savings, the performance penalty of disintegration is not well studied. This paper presents the first characterization, to our knowledge, of disintegration performance penalty across a diverse suite of applications. Unsurprisingly, applications with high speedups on monolithic systems continue to scale well on disintegrated systems, and vice versa. However, the disintegration slowdown compared to an equivalently sized monolith exhibits high variance across applications, with some achieving just over half the performance. Why do some applications get a performance per dollar win, while others lose? Through regression analysis, we find that metrics relating to the network-on-package bandwidth and data sharing correlate with disintegration slowdown. Programmers were already cautioned against shared mutable data on monolithic systems, yet data sharing is unavoidable in many applications. These applications will be disproportionately harmed in the disintegrated future.

关键词： silicon interposer multi-chip module disintegration slowdown chiplets data sharing regression

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Achieving Spaceworthiness for Large-Size LTCC Packaging of Microwave MCM

Achieving Spaceworthiness for Large-Size LTCC Packaging of M...

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2023 IEEE Microwaves, Antennas, and Propagation Conference, MAPCON 2023

作者： Prajapati, Ishwarlal Hegde, Ravindra K. Pandya, Shilpa Lal, Ajay Kumar Ahmedabad India

ISBN: (纸本)9798350328264

This paper describes the various methodologies for realization of microwave subsystems through packaging of multiple bare MMICs. The use of LTCC substrate for packaging of hermetic multi-chip modules (MCM) has given significant benefits in terms of miniaturization and mass reduction. However, it poses several challenges for assembly and hermetic sealing of these large-size (>35 mm in both dimensions) LTCC modules. Various techniques for assembly and hermetic sealing were attempted and their outcomes are summarized. © 2023 IEEE.

关键词： Epoxy sealing hermetic sealing Laser sealing LTCC multi-chip module

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Converged RF Phased Arrays Enabled by Silicon Photonics

Converged RF Phased Arrays Enabled by Silicon Photonics

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IEEE International Symposium on Phased Array Systems and Technology (PAST)

作者： Hoff, Michael T. Kedia, Amit Nguyen, Nhat Paddison, Robert Stevens, Rick C. Lockheed Martin Corp Adv Technol Labs Atlanta GA USA Ayar Labs Santa Clara CA USA

ISBN: (数字)9781665441667

ISBN: (纸本)9781665441667

This paper proposes a converged-aperture architecture to enable dynamic reconfiguration of spectral access between platform mission functions. Based on phased-array apertures, intra-platform data throughputs required to support the envisioned architecture are discussed, and integrated photonic transceivers are put forward as a critical enabling technology.

关键词： converged apertures integrated photonics millimeter wave system of systems multi-chip module edge sensing

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