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55th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Pratheek, B. Jawalkar, Neha Basu, Arkaprava Indian Inst Sci Bangalore Karnataka India

ISBN: (数字)9781665462723

ISBN: (纸本)9781665462723

multi-chip module (MCM) designs have emerged as a key technique to scale up a GPU's compute capabilities in the face of slowing transistor technology. However, the disaggregated nature of MCM GPUs with many chiplets connected via in-package interconnects leads to non-uniformity. We explore the implications of MCM's non-uniformity on the GPU's virtual memory. We quantitatively demonstrate that an MCM-aware virtual memory system should aim to (1) leverage aggregate TLB capacity across chiplets while limiting accesses to L2 TLB on remote chiplets, (2) reduce accesses to page table entries resident on a remote chiplet's memory during page walks. We propose MCM-aware GPU virtual memory (MGvm) that leverages static analysis techniques, previously used for thread and data placement, to map virtual addresses to chiplets and to place the page tables. At runtime, MGvm balances its objective of limiting the number of remote L2 TLB lookups with that of reducing the number of remote page table accesses to achieve good speedups (52%, on average) across diverse application behaviors.

关键词： Graphics Processing Units multi-chip module chiplet Virtual Memory Address Translation Page Table Walkers Translation Look-aside Buffers

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Design and Development of a Low Phase Noise multi-Output Millimeter-Wave Frequency Synthesizer with High Output Power 22

Design and Development of a Low Phase Noise Multi-Output Mil...

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IEEE 22nd Annual Wireless and Microwave Technology Conference (WAMICON)

作者： Bhattacharyya, Shrija Tolani, Harshita Bhattacharya, Anamiya Shaik, Latheef A. Bhadoria, Mahendra P. S. Chakraborty, Prantik Rao, Ch. V. N. Jyoti, Rajeev Space Applicat Ctr Microwave Remote Sensors Area Ahmadabad Gujarat India

ISBN: (纸本)9781665421959

This paper describes the design and realization of a compact, low phase noise, multi-output millimeter-wave frequency synthesizer (FS) using a combination of fractional-N Phase Locked Loop (PLL) and direct frequency synthesis for the generation of tunable local oscillator (LO) signals centered at 37.56GHz and 5.07GHz. Input reference for coherent signal generation is derived from a highly stable Temperature Compensated Crystal Oscillator (TCXO). High power GaAs Monolithic Microwave Integrated Circuits (MMICs) accommodated within a compact multi-chip Drop-in module (DIM) provide 1.2W CW output at 37.56GHz with proper thermal management to mitigate localized heat dissipation. Measured results demonstrate output power of +30.8dBm at 37.56GHz with phase noise of -78.36dBc/Hz at 1KHz offset and +14.3dBm at 5.07GHz with phase noise of -89.68dBc/Hz at 1KHz offset and close-to-carrier spurious below 60dBc.

关键词： Ka-band loop filter MMIC multi-chip module output power PLL phase noise spurious

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Optimization of fin layout in liquid-cooled microchannels for multi-core chips

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CASE STUDIES IN THERMAL ENGINEERING 2023年 41卷

作者： Zhang, Jian Guo, Wenyong Xie, Zhihui Guan, Xiaonan Qu, Xuejian Ge, Yanlin Naval Univ Engn Coll Power Engn Wuhan 430033 Peoples R China Wuhan Inst Technol Inst Thermal Sci & Power Engn Wuhan 430205 Peoples R China Wuhan Inst Technol Sch Mech & Elect Engn Wuhan 430205 Peoples R China

When the dense pin-fins array distributed uniformly is used to dissipate the non-uniform heat source, it is easy to generate excessive cooling at the non-hot spot, which leads to unnecessary heat dissipation loss. In this study, a three-dimensional model of a multi-core chip-microchannel heat sink is established. Fin layout in the chip-microchannel is optimized under the conditions of non-uniform power-partition chip based on constructal theory. The total volume of fins in a channel is selected as the constraint condition. A genetic algorithm is used to seek the optimal construct. Comparing the optimal fin layout with the dense pin-fins array, the results demonstrate that the maximum temperature can be reduced by 6.75 K when Re number is 750, and the total pressure loss can be reduced by 54.1% when Re number is 750. Namely, under the condition of non-uniform heat source, the fins with a certain total volume were distributed reasonably, which can maintain the optimal balance of heat dissipation capacity and heat dissipation cost, so that the accurate and efficient thermal design is realized, and the better comprehensive benefits are obtained.

关键词： Constructal theory Fin layout multi-chip module Microchannels Thermal reliability

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GPU Domain Specialization via Composable On-Package Architecture

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2022年第1期19卷 4-4页

作者： Fu, Yaosheng Bolotin, Evgeny Chatterjee, Niladrish Nellans, David Keckler, Stephen W. NVIDIA Corp 2788 San Tomas Expy Santa Clara CA 95051 USA

As GPUs scale their low-precision matrix math throughput to boost deep learning (DL) performance, they upset the balance between math throughput and memory system capabilities. We demonstrate that a converged GPU design trying to address diverging architectural requirements between FP32 (or larger)-based HPC and FP16 (or smaller)-based DL workloads results in sub-optimal configurations for either of the application domains. We argue that a Composable On-PAckage GPU (COPA-GPU) architecture to provide domain-specialized GPU products is the most practical solution to these diverging requirements. A COPA-GPU leverages multi-chip-module disaggregation to support maximal design reuse, along with memory system specialization per application domain. We show how a COPA-GPU enables DL-specialized products by modular augmentation of the baseline GPU architecture with up to 4x higher off-die bandwidth, 32x larger on-package cache, and 2.3x higher DRAM bandwidth and capacity, while conveniently supporting scaled-down HPC-oriented designs. This work explores the microarchitectural design necessary to enable composable GPUs and evaluates the benefits composability can provide to HPC, DL training, and DL inference. We show that when compared to a converged GPU design, a DL-optimized COPA-GPU featuring a combination of 16x larger cache capacity and 1.6x higher DRAM bandwidth scales per-GPU training and inference performance by 31% and 35%, respectively, and reduces the number of GPU instances by 50% in scale-out training scenarios.

关键词： GPU computing multi-chip module

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Designing Virtual Memory System of MCM GPUs 22

Designing Virtual Memory System of MCM GPUs

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Proceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture

作者： Pratheek B Neha Jawalkar Arkaprava Basu Indian Institute of Science Bangalore India

ISBN: (纸本)9781665462723

multi-chip module (MCM) designs have emerged as a key technique to scale up a GPU's compute capabilities in the face of slowing transistor technology. However, the disaggregated nature of MCM GPUs with many chiplets connected via in-package interconnects leads to *** explore the implications of MCM's non-uniformity on the GPU's virtual memory. We quantitatively demonstrate that an MCM-aware virtual memory system should aim to 1 leverage aggregate TLB capacity across chiplets while limiting accesses to L2 TLB on remote chiplets, 2 reduce accesses to page table entries resident on a remote chiplet's memory during page walks. We propose MCM-aware GPU virtual memory (MGvm) that leverages static analysis techniques, previously used for thread and data placement, to map virtual addresses to chiplets and to place the page tables. At runtime, MGvm balances its objective of limiting the number of remote L2 TLB lookups with that of reducing the number of remote page table accesses to achieve good speedups (52%, on average) across diverse application behaviors.

关键词： graphics processing units multi-chip module chiplet virtual memory address translation page table walkers translation look-aside buffers

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A D-Band Radio-on-Glass module for Spectrally-Efficient and Low-Cost Wireless Backhaul

A D-Band Radio-on-Glass Module for Spectrally-Efficient and ...

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IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

作者： Singh, Amit Sayginer, Mustafa Holyoak, Michael J. Weiner, Joseph Kimionis, John Elkhouly, Mohamed Baeyens, Yves Shahramian, Shahriar Nokia Bell Labs Murray Hill NJ 07974 USA

ISBN: (数字)9781728168098

ISBN: (纸本)9781728168098

D-Band Radio-on-Glass (RoG) modules combining two highly integrated SiGe BiCMOS transceivers (TRX) with a record low-loss glass interposer technology are presented. The ICs operate at 115-155 GHz (Low-Band) and 135-170 GHz (High-Band). In this frequency range, a transmitter Psat up to 13 dBm and an average receiver NF of 8.5 dB is achieved. The integrated module supports TX constellations up to 512-QAM (2.2% EVM at 2 dBm output, 145 GHz) and data-rates up to 42 Gb/s (128-QAM). Measurements mimicking a 250-meter wireless-link demonstrate a maximum data-rate of 36 Gb/s using 64-QAM. The RoG modules represent the first low-cost and highly integrated solution for spectrally efficient backhaul systems in D-Band.

关键词： 5G D-Band beyond 100GHz Radio-on-Glass glass interposer downconversion mixer LNA multi-chip module mm-wave transceiver upconversion mixer wireless backhaul

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Development of multi-chip module-D Technology-Testchip

Development of Multi-Chip Module-D Technology-Testchip

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28th Symposium on Microelectronics Technology and Devices

作者： Freitas, Wilson Flacker, Alexander Adamo, Cristina B. Rotondaro, Antonio L. P. Renato Archer Ctr Informat Technol Campinas SP Brazil

ISBN: (纸本)9781479905188

multi-chip modules enable combining different integrated circuits with passive components leading to advantages in size, performance and cost. This paper presents the design of a testchip which was planned to extend the characterization of the process parameters for the development of MCM-D technology. It was made using Virtuoso Cadence Software, with minimum dimension of 20 mu m, resulting in four mask layers.

关键词： multi-chip module passive components photomask testchip

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Impact Of Device Parametric Tolerances On Current Sharing Behavior Of A Sic Half-Bridge Power module

Impact Of Device Parametric Tolerances On Current Sharing Be...

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作者： Grace R. Watt Virginia Polytechnic Institute and State University

学位级别：硕士

This paper describes the design, construction, and testing of advanced power devices for use in electric vehicles. Power devices are necessary to supply electricity to different parts of the vehicle; for example, energy is stored in a battery as direct current (DC) power, but the motor requires alternating current (AC) power. Therefore, power electronics can alter the energy to be delivered as DC or AC. In order to carry more power, multiple devices can be used together just as 10 people can carry more weight than 1 person. However, because the devices are not perfect, there can be slight differences in the performance of one device to another. One device may have to carry more current than another device which could cause failure earlier than intended. In this research project, multiple power devices were placed into a package, or "module." In a control module, the devices were selected with similar properties to one another. In an experimental module, the devices were selected with properties very different from one another. It was determined that the when the devices were 17.7% difference, there was 119.9 µJ more energy loss and it was 22.2°C hotter than when the difference was only 0.6%. However, the severity of the difference was dependent on how multiple device characteristics interacted with one another. It may be possible to compensate some of the impact of device differences in one characteristic with opposing differences in another device characteristic.

关键词： SiC MOSFET power module packaging flexible PCB current sharing symmetrical direct bonded copper (DBC) layout diode-less module multi-chip module device parametric tolerances package parasitics vertical GaN

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Instrumentation of Twin-MCMs based mutual-test

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MICROELECTRONICS JOURNAL 2021年 114卷 105108-105108页

作者： Peter, Wang Shun Shen Yin-Tien, Wang Choung-Lii, Chao Wei-Bin, Yang JTAG Technol BV Boschdijk 50 NL-5612 AN Eindhoven Netherlands Tamkang Univ Dept Mech Engn 151 Ying Chuan Rd Taipei 25137 Taiwan

This paper presents advanced data collection methods using boundary scan based vector analysis, developed to debug manufacturing defects on cell based IC's such as JTAG compliant dice. Advantageously, they provide solutions to unknown dice by arranging identically designed multi-chip modules (MCM), to thereby diagnose possible flaws on dice due to thermal stresses on substrates as well as cold or hot soldering of the bumps, of which introducing fatigue and cracks, etc., defectives, and this system potentially to repair the problematic MCMs after trouble-shooting the twin-MCMs through self and mutual testing to validate the Known Good Dice (KGD).

关键词： multi-chip module chiplet Interposer Substrate Know-good-die Flip-chip Boundary scan JTAG Wafer scale integration

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Impact of Device Parametric Tolerances on Current Sharing Behavior of a SiC Half-Bridge Power module

Impact of Device Parametric Tolerances on Current Sharing Be...

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作者： Watt, Grace R. Virginia Tech | University

This paper describes the design, fabrication, and testing of a 1.2 kV, 6.5 mΩ, half-bridge, SiC MOSFET power module to evaluate the impact of parametric device tolerances on electrical and thermal performance. Paralleling power devices increases current handling capability for the same bus voltage. However, inherent parametric differences among dies leads to unbalanced current sharing causing overstress and overheating. In this design, a symmetrical DBC layout is utilized to balance parasitic inductances in the current pathways of paralleled dies to isolate the impact of parametric tolerances. In addition, the paper investigates the benefits of flexible PCB in place of wire bonds for the gate loop interconnection to reduce and minimize the gate loop inductance. The balanced modules have dies with similar threshold voltages while the unbalanced modules have dies with unbalanced threshold voltages to force unbalanced current sharing. The modules were placed into a clamped inductive DPT and a continuous, boost converter. Rogowski coils looped under the wire bonds of the bottom switch dies to observe current behavior. Four modules performed continuously for least 10 minutes at 200 V, 37.6 A input, at 30 kHz with 50% duty cycle. The modules could not perform for multiple minutes at 250 V with 47.7 A (23 A/die). The energy loss differential for a ~17% difference in threshold voltage ranged from 4.52% (~10 µJ) to -30.9% (~30 µJ). The energy loss differential for a ~0.5% difference in V_th ranged from -2.26% (~8 µJ) to 5.66% (~10 µJ). The loss differential was dependent on whether current unbalance due to on-state resistance compensated current unbalance due to threshold voltage. While device parametric tolerances are inherent, if the higher threshold voltage devices can be paired with devices that have higher on-state resistance, the overall loss differential may perform similarly to well-matched dies. Lastly, the most consistently performing unbalanced module with 17.7% d

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