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检索条件"主题词=Multi-Chip Module"

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Approximate Pattern Matching for On-chip Interconnect Traffic Prediction 20

Approximate Pattern Matching for On-Chip Interconnect Traffi...

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ACM International Conference on Parallel Architectures and Compilation Techniques (PACT)

作者： Adhinarayanan, Vignesh Feng, Wu-chun Virginia Tech Blacksburg VA 24061 USA

ISBN: (纸本)9781450380751

Emerging multi-chip module GPUs (MCM-GPUs) expend over 17% of the total power budget on chip interconnects and this fraction is expected to increase as chip size increases. Towards proactively managing the power consumption of these interconnects, we propose approximate pattern matching to predict future interconnect traffic from past observations. Compared to past prediction techniques such as Markov model (MM) and history table (HT), our proposed technique reduces average prediction error to 2.66% from 7.11% and 3.83% for MM and HT, respectively.

关键词： data movement phase prediction multi-chip module chiplet interconnects

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Application of AOI light source modes in multi-chip modules inspection 19

Application of AOI light source modes in multi-chip modules ...

引用

19th International Conference on Electronic Packaging Technology (ICEPT)

作者： Wu, Yilong Wen, Junling Zhang, Pingsheng China Elect Technol Grp Corp Res Inst 29 Microwave Circuit Integrat Ctr Chengdu Sichuan Peoples R China

ISBN: (纸本)9781538663868

Automated optical inspection (AOI) is a way of checking the assembly quality of printed circuit boards using machine vision techniques and becomes an indispensable part of the PCBA assembly process in recent years. Due to its consistent and repeatable nature, AOI is an effective process control tool. However, when AOI was applied on substrate, die or bond wire inspection in multi-chip modules, pseudo-defect or false call occurred commonly. In this paper, the influences of light source modes on probability of detection were studied and several using advices were proposed. The results showed that when using proper light source, best contrast of the detected image could be got and thus the missing defect rate of MCM could be reduced.

关键词： automated optical inspection light source mode multi-chip module

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A 4 mm toroidal microtransformer built with wire bonding and MCM technologies 34

A 4 mm toroidal microtransformer built with wire bonding and...

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34th Symposium on Microelectronics Technology and Devices (SBMicro)

作者： do Nascimento, Fellype Telles, Camilla C. C. Rocha, Marinalva M. Teixeira, Ricardo C. NCSH Ctr Informat Technol Renato Archer Campinas SP Brazil NEE Ctr Informat Technol Renato Archer Campinas SP Brazil

ISBN: (纸本)9781728119090

Manufacturing of small-scale magnetic devices is a subject that is not yet fully consolidated. Then the development process - design, fabrication and characterization - of microtransformers continues as object of studies for several applications. In this work it is presented the development and characterization steps of a four mm diameter toroidal microtransformer built using wire bonding and multi-chip module (MCM) technologies. The device has a 19:1 turn ratio, with 31 mu m diameter aluminum wire bond around the top of a MnZn ferrite core. The wire bonds are connected to thin film gold tracks with similar to 3.5 mu m thickness at the bottom in order to complete the windings. The main parameters measured were the inductances and resistances of primary and secondary windings, and also the series-aiding and series-opposing inductances, all of them in the frequency range from 10 kHz to 2 MHz. With the results from those measurements the quality factors, mutual inductance and coupling coefficients were obtained. The inductance values of both windings are in agreement with expected ones. The device shows a good coupling coefficient and acceptable quality factors. The results show that it is feasible to build microtransformers with wire bonding onto an MCM substrate.

关键词： microtransformer wire bonding multi-chip module energy harvesting

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A reconfigurable antenna element for improved physical layer control

A reconfigurable antenna element for improved physical layer...

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USNC-URSI Radio Science Meeting / IEEE International Symposium on Antennas and Propagation (AP-S)

作者： McMahon, Benjamin Lapierre, Randall Westafer, Ryan S. Lee, R. Todd BAE Syst Fast Labs Merrimack NH 01803 USA GTRI Adv Concepts Lab Atlanta GA USA

ISBN: (纸本)9781728106922

A new reconfigurable phased array antenna element is described. This element operates at X-band and provides digital control of the effective antenna structure, and therefore, its far field pattern, frequency response, polarization, etc. This presents an opportunity to improve the performance of software-defined or cognitive radio systems for which improved reconfigurable filtering is needed [1-2]. Because this reconfiguration occurs at the antenna and outside the front end, it has the potential to increase the dynamic range available to a system when operating in close proximity to other users.

关键词： phased array GaAs MCM multi-chip module reconfigurable AESA

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Application of AOI light source modes in multichip modules inspection

Application of AOI light source modes in multichip modules i...

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第十九届国际电子封装技术会议(ICEPT 2018)

作者： Yilong WU Junling WEN Pingsheng ZHANG Microwave Circuit Integration Center The 29th Research Institute of China Electronics Technology Group Corporation Chengdu China

Automated optical inspection(AOI)is a way of checking the assembly quality of printed circuit boards using machine vision techniques and becomes an indispensable part of the PCBA assembly process in recent *** to its consistent and repeatable nature,AOI is an effective process control ***,when AOI was applied on substrate,die or bond wire inspection in multi-chip modules,pseudo-defect or false call occurred *** this paper,the influences of light source modes on probability of detection were studied and several using advices were *** results showed that when using proper light source,best contrast of the detected image could be got and thus the missing defect rate of MCM could be reduced.

关键词： automated optical inspection light source mode multi-chip module

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Microfabricated ISM Band Inductors using MCM-D Technology over Alumina Substrates 33

Microfabricated ISM Band Inductors using MCM-D Technology ov...

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33rd Symposium on Microelectronics Technology and Devices (SBMicro)

作者： Adamo, Cristina B. Flacker, Alexander Medeiros, Rafael C. Castillo, Sergio O. Ponchet, Andre da F. Teixeira, Ricardo C. Renato Archer Ctr Informat Technol Elect Packaging Div Campinas SP Brazil Renato Archer Ctr Informat Technol Elect Prod Anal & Qualificat Div Campinas SP Brazil Renato Archer Ctr Informat Technol Hardware Concept Div Campinas SP Brazil

ISBN: (纸本)9781538683910

Current trend on electronics seek devices with more functionalities integrated on a smaller footprint. multi-chip module technology based on thin films deposition (MCM-D) is one enabling technology that can achieve such demand. In this paper authors present a technological sequence to fabricate inductors onto an NICNI-D device that can he integrated with other passive components aiming for higher integration compared to PCB technologies and RFID and/or IoT devices. We found Q values for unlicensed ISM (industrial, scientific and medical applications) bands of the fabricated devices present specs similar to commercially available components.

关键词： ISM bands inductors multi-chip module thin films

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Embedded Silicon Fan-Out (eSiFO): A Promising Wafer Level Packaging Technology for multi-chip and 3D System Integration 68

Embedded Silicon Fan-Out (eSiFO): A Promising Wafer Level Pa...

引用

68th IEEE Electronic Components and Technology Conference (ECTC)

作者： Ma, Shuying Wang, Jiao Zhen, Fengxia Xiao, Zhiyi Wang, Teng Yu, Daquan Huantian Technol Kunshan Elect Co Ltd 112 LongTeng RDEcon & Tech Developmet Zone Kunshan 215300 Jiangsu Peoples R China

ISBN: (纸本)9781538649985

The demand for miniaturized package size, higher performance and integration density, lower power consumption, and lower manufacturing cost drives the development of various new packaging technologies, such as WLP, 2.5D interposer, 3D WLCSP etc. Recently, Fan-Out Wafer Level Package (FOWLP) has aroused more and more interest since it emerged as a successful technology in providing the solution to meet advanced system packaging and integration requirements. FOWLP has also become a key-enabling technology for multi-chip and 3D system integration. Embedded silicon fan-out (eSiFO (R)) technology developed by Huatian group was a low cost FOWLP technology, which eliminates molding, temporary bonding and de-bonding in the process flow. The eSiFO (R) technology for single chip with a high yield of 99.5% was reported. In this paper, the development of eSiFO (R) technology for multi-chip and 3D system integration was reported. One package in the size of 5.2x4.0 mm(2) and containing 5 chips has been successfully produced. Small warpage of similar to 1mm for eSiFO (R) 300mm wafer was achieved even with 2 layer thick RDLs. Another 3D-Integration package based on the eSiFO (R) technology has also been successfully demonstrated, where two dies were stacked on the top of the eSiFO (R) wafer by die placement and mass reflow processes. For the 3D eSiFO (R) SiP package, the size and thickness was 4.1x4.1mm, and 0.375 mm respectively. One RDL was formed on both front and backside of the eSiFO (R). The interconnection between the embedded chip and the stacked chips was made through micro bumps and through-silicon vias (TSVs) located in the fan-out area of the carrier wafer. The manufactured packages have shown good electrical yield and passed standard reliability tests.

关键词： Fan-out eSiFO 3D integration multi-chip module

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Embedded Silicon Fan-Out (eSiFO): A Promising Wafer Level Packaging Technology for multi-chip and 3D System Integration

Embedded Silicon Fan-Out (eSiFO): A Promising Wafer Level Pa...

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IEEE Electronic Components and Technology Conference

作者： Shuying Ma Jiao Wang Fengxia Zhen Zhiyi Xiao Teng Wang Daquan Yu Huantian Technology (Kunshan) Electronics Co. Ltd. Kunshan Jiangsu China Huantian Technol. (Kunshan) Electron. Co. Ltd. Kunshan China

The demand for miniaturized package size, higher performance and integration density, lower power consumption, and lower manufacturing cost drives the development of various new packaging technologies, such as WLP, 2.5D interposer, 3D WLCSP etc. Recently, Fan-Out Wafer Level Package (FOWLP) has aroused more and more interest since it emerged as a successful technology in providing the solution to meet advanced system packaging and integration requirements. FOWLP has also become a key-enabling technology for multi-chip and 3D system integration. Embedded silicon fan-out (eSiFO?) technology developed by Huatian group was a low cost FOWLP technology, which eliminates molding, temporary bonding and de-bonding in the process flow. The eSiFO? technology for single chip with a high yield of 99.5% was reported. In this paper, the development of eSiFO? technology for multi-chip and 3D system integration was reported. One package in the size of 5.2×4.0 mm~2 and containing 5 chips has been successfully produced. Small warpage of ~lmm for eSiFO? 300mm wafer was achieved even with 2 layer thick RDLs. Another 3D-Integration package based on the eSiFO? technology has also been successfully demonstrated, where two dies were stacked on the top of the eSiFO? wafer by die placement and mass reflow processes. For the 3D eSiFO? SiP package, the size and thickness was 4.1×4.1mm, and 0.375 mm respectively. One RDL was formed on both front and backside of the eSiFO?. The interconnection between the embedded chip and the stacked chips was made through micro bumps and through-silicon vias (TSVs) located in the fan-out area of the carrier wafer. The manufactured packages have shown good electrical yield and passed standard reliability tests.

关键词： Fan-out eSiFO 3D integration multi-chip module

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Polymer Waveguide-Based Reservoir Computing 24th

Polymer Waveguide-Based Reservoir Computing

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24th International Conference on Neural Information Processing (ICONIP)

作者： Heroux, Jean Benoit Numata, Hidetoshi Nakano, Daiju IBM Res Kawasaki Kanagawa 2120032 Japan

ISBN: (纸本)9783319701363;9783319701356

Polymer waveguide optical interconnect technology, in which VCSEL and photodiode chip arrays are flip-mounted on an organic carrier to fabricate optical multi-chip modules, has been intensively developed over the last 15 years for data transfer applications in high performance computers. In that application, multiple-channel data signals transmitted to and from CPU and memory components in a system are converted into optical signals for short range, high density, high speed, low power and low cost digital communication. In this work we explore how these efforts could be leveraged to fabricate a compact, fully integrated photonic reservoir computing module with several devices potentially operating in parallel. We present experimental results of low optical loss in a crossing structure as well as good performance simulated with realistic parameters of a time-multiplexed reservoir performing a signal recovery task.

关键词： Reservoir computing Photonics VCSEL Waveguide Array multi-chip module

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A 3D Packaging Technology for Acoustically Optimized Integration of 2D CMUT Arrays and Front End Circuits

A 3D Packaging Technology for Acoustically Optimized Integra...

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IEEE International Ultrasonics Symposium (IUS)

作者： Savoia, Alessandro Stuart Mauti, Barbara Caliano, Giosue Bardelli, Roberto Toia, Fabrizio Quaglia, Fabio Matrone, Giulia Piastra, Marco Ramalli, Alessandro Roma Tre Univ Dept Engn Rome Italy ST Microelect Agrate Brianza Italy Univ Pavia Dept Elect Comp & Biomed Engn Pavia Italy Univ Florence Dept Informat Engn Florence Italy

ISBN: (纸本)9781538633830

As compared to piezoelectric technology, MEMS technology employed for Capacitive Micromachined Ultrasonic Transducer (CMUT) fabrication provides increased compatibility with 3D packaging methods, enabling the possible development of advanced transducer-electronics multi-chip modules (MCM) for medical imaging applications. In this paper, an acoustically optimized 3D packaging method for the interconnection of Reverse-Fabricated 2D CMUT arrays and front end ICs using a wafer-level compatible process is presented. The developed packaging method uses Cu pillars and Sn-Ag solder reflow for electrical interconnection, and patterned Benzocyclobutene (BCB) for mechanical bonding. Process parameters were optimized by analyzing the acoustic behavior of a CMUT supported by a BCB film laying on a silicon substrate using Finite Element Modeling (FEM). Dummy CMUT and ASIC wafers were processed and MCMs were assembled following a chip-to-chip bonding approach using the optimized process parameters. Electrical characterization of the MCMs demonstrated successful contact across the entire fabricated devices. Probe head prototypes were assembled and pulse-echo experiments were carried out using the MCM surface as a reflector to verify the effectiveness of the optimization on the acoustic behavior of the device.

关键词： CMUT 3D packaging acoustic optimization multi-chip module Cu pillars BCB Reverse Fabrication Process FEM

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