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26th Annual IEEE Applied power Electronics Conference and Exposition (APEC)

作者： Al Razi, Imam Huitink, David R. Peng, Yarui Univ Arkansas Comp Sci & Comp Engn Dept Fayetteville AR 72701 USA Univ Arkansas Mech Engn Dept Fayetteville AR 72701 USA

ISBN: (纸本)9781728189499

High-performance multi-chip power modules (MCPMs) are essential for high-density and efficient power conversion. Meanwhile, the chip layout and design methodology fundamentally determine thermal and reliability performance. Hign-density power modules typically consist of wide-bandgap (WBG) semiconductor die, soldering materials, baseplate, and heatsink packed on a single substrate. To a great extent, the reliability of power modules depends on these material electro-thermal-mechanical properties during variable operating conditions. Appropriate thermal management can reduce stress and enhance the component lifetime by controlling junction temperature. In this work, a fast, generic, and scalable transient thermal model has been developed for the powerSynth layout synthesis tool to optimize layer material, thickness, and layer stack configurations by minimizing thermal stress due to thermal cycling. This model has shown approximately 3,489 times speed up with less than 10% mismatch compared to ANSYS simulation. A powerSynth-guided design-for-reliability computer-aided design (CAD) flow is presented to optimize both the layer stack and the layout simultaneously.

关键词： powerSynth Transient Thermal Model multi-chip power module Reliability Optimization Phase Change Material

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A Layout Optimization Method to Reduce Commutation Inductance of multi-chip power module Based on Genetic Algorithm

A Layout Optimization Method to Reduce Commutation Inductanc...

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IEEE Workshop on Wide Bandgap power Devices and Applications in Asia (WiPDA Asia)

作者： Zhou, Yu Chen, Yu Gao, Hongyi Li, Chengmin Luo, Haoze Li, Wuhua He, Xianging Zhejiang Univ Coll Elect Engn Hangzhou Peoples R China

ISBN: (纸本)9781665418515

This paper describes an automatic optimization method for multi-chip power module (MCPM) layout based on template generation and evolutionary computation techniques. The method is developed with particular emphasis on reducing the commutation inductance and balancing the branch inductances among paralleled chips of the module. An automatic layout generation from netlist and design constraints to ready-to-fabricate prototype is carried using two-step graph-based template generation and genetic algorithm-based sizing approach. The method employs the built-in multi-port discrete circuit model for fast evaluation of layout inductance for parasitics extraction. An analytical model is also established to assist the design of embedded snubber in the post-process stage. The layout design of a 4-chip SiC module is demonstrated. Both the simulations and the experiments are conducted to illustrate the advantage of performing the automatic optimization from the initial stage of the design process.

关键词： multi-chip power module layout optimization parasitic inductance genetic algorithm snubber design

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Sensitivities in High-Bandwidth, High-Current Shunt Measurements for Silicon-Carbide multi-chip power modules 37

Sensitivities in High-Bandwidth, High-Current Shunt Measurem...

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37th Annual IEEE Applied power Electronics Conference and Exposition (APEC)

作者： New, Christopher D. Lemmon, Andrew N. DeBoi, Brian T. Univ Alabama Dept Elect & Comp Engn Tuscaloosa AL 35487 USA

ISBN: (纸本)9781665406895;9781665406888

Emerging high-current Silicon Carbide (SiC) multi-chip power modules (MCPMs) are challenging traditional current measurement techniques used for device characterization. Coaxial shunts are typically employed for low-current device characterization measurements. However, these devices introduce non-negligible insertion inductance that is problematic when used for characterizing high- current MCPMs. Consequently, many researchers are adopting a "bar-style" shunt for high-current MCPM characterization. The bar-style shunt enables designers to maintain wide bussing throughout the characterization circuitry. However, one challenge with the barstyle shunt is its significantly lower resistance compared to a coaxial shunt, which reduces the signal-to- noise ratio (SNR). The poor SNR makes the bar-style shunt susceptible to environmental factors. One primary sensitivity that has been identified is the coaxial connection between the shunt and the oscilloscope. This manuscript evaluates the sensitivity of these connections and provides recommendations for performing high-fidelity current measurements using the bar-style shunt.

关键词： double pulse test multi-chip power module current measurement

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Common Source Inductance Compensation Technique for Dynamic Current Balancing in SiC MOSFETs Parallel Operations 38

Common Source Inductance Compensation Technique for Dynamic ...

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IEEE Applied power Electronics Conference and Exposition (APEC)

作者： Zhang, Boyi Wang, Ruxi Barbosa, Peter Tsai, Yu-Hsuan Wang, Wen-Sheng Lai, Wen-Shang Delta Elect Amer Ltd 5101 Davis Dr Res Triangle Pk NC 27709 USA Delta Elect Inc 16 Tungyuan Rd Taoyuan 320023 Taiwan

ISBN: (纸本)9781665475396

In high-current applications such as traction inverters, SiC MOSFETs are paralleled to increase the current capability. One major issue in paralleling SiC MOSFETs is the dynamic current unbalance. The unbalanced dynamic current could lead to severe device and system failures. It was well known that one of the root causes of dynamic current unbalance is parasitic parameter unbalance due to asymmetrical layout. In this paper, the impact of different parasitic parameters in circuit layout on current sharing is identified. Based on the analysis, a common source inductance (CSI) compensation technique is proposed for SiC MOSFETs in parallel operations to balance the dynamic current during the switching transient. With the proposed technique, the dynamic current among paralleled switches is evenly distributed even when the layout is not symmetrical. The improved current sharing is achieved by designing the common source inductance of each paralleled device inversely proportional to the power loop inductance. Because of the balanced dynamic current, the reliability of the circuit with the proposed layout can be significantly improved. The proposed technique is an easy-to-implement design that requires no additional components. Two types of prototypes are built to verify the proposed technique: A half-bridge configuration with SiC discrete devices in parallel and a multi-chip power module with SiC dies in parallel. The proposed technique is proven effective in both cases.

关键词： Device paralleling dynamic current balance multi-chip power module traction inverters WBG devices

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Hierarchical Layout Synthesis and Design Automation for 2.5D Heterogeneous multi-chip power modules 11

Hierarchical Layout Synthesis and Design Automation for 2.5D...

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11th Annual IEEE Energy Conversion Congress and Exposition (ECCE)

作者： Al Razi, Imam Le, Quang Mantooth, H. Alan Peng, Yarui Univ Arkansas Comp Sci & Comp Engn Dept Fayetteville AR 72701 USA Univ Arkansas Dept Elect Engn Fayetteville AR 72701 USA

ISBN: (纸本)9781728103952

multi-chip power module (MCPM) layout design automation has been identified as one of the primary research interests in the power electronics community with the advent of wide bandgap circuits. MCPM physical design requires a time-consuming iterative procedure that is so far explored manually based on the experience of the designers. Though the number of components and routing layers is limited in power electronics, careful physical design is required because of thermal and reliability issues. In this paper. the benefits of a hierarchical design methodology are demonstrated over the state-of-the-art approaches. We propose a generic, scalable, and efficient algorithm to automate not only 2D but also 2.5D (multiple substrates in a planar package) and 3D (multiple device layers slacked on the same substrate) heterogeneous MCPM layouts considering hierarchy. A complete optimization approach for a Mal-bridge 2.5D power module is demonstrated using hardware-validated electrical and thermal models.

关键词： powerSynth corner stitch constraint graph multi-chip power module algorithms hierarchy 2.5D power module layout optimization

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Cancellation of Leakage Currents through power module Baseplate Capacitance 34

Cancellation of Leakage Currents through Power Module Basepl...

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34th Annual IEEE Applied power Electronics Conference and Exposition (APEC)

作者： Brovont, Aaron D. Lemmon, Andrew N. New, Christopher Nelson, Blake W. DeBoi, Brian T. Univ Alabama Dept Elect & Comp Engn Tuscaloosa AL 35487 USA

ISBN: (纸本)9781538683309

The fast edge rates achievable by wide-bandgap semiconductors can produce significant common-mode leakage currents through the baseplates of encompassing power modules. Such common-mode currents can lead to elevated electromagnetic signatures. This paper provides a theoretical treatment of this common-mode behavior for a typical SIC half-bridge multichip power module in the context of a half-bridge inverter. A common-mode equivalent model is produced that identifies the distribution of the parasitic baseplate capacitance across the module terminals as the principal factor that controls the leakage current through the module baseplate. Furthermore, the model predicts that this leakage current can be manipulated and even canceled out by achieving a prescribed distribution of said baseplate capacitance for the system under investigation. These predictions are validated by a set of empirical studies in which compensating capacitors are affixed to the external terminals of a commercial multi-chip power module comprising a half-bridge inverter. The model predictions are shown to be in good agreement with the measured behavior of this system.

关键词： Baseplate capacitance conducted EMI leakage current multi-chip power module wide-bandgap

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Utilization of power module Baseplate Capacitance for Common-Mode EMI Filter Reduction

Utilization of Power Module Baseplate Capacitance for Common...

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IEEE Electric Ship Technologies Symposium (ESTS) - Emerging Technologies for Future Electric Ships

作者： Brovont, Aaron D. Lemmon, Andrew N. Univ Alabama Dept Elect & Comp Engn Tuscaloosa AL 35487 USA

ISBN: (纸本)9781538675601

Interest in the electromagnetic compatibility of power electronic systems continues to accelerate due to continued advancement in application and technological drivers such as electrified transportation and maturation of wide-bandgap semiconductors, respectively. A parasitic coupling that is known to play a significant role in the generation of conducted emissions in power electronic systems is the capacitance between the power switches and their heat sink. This paper explores the use of this parasitic capacitance to reduce the CM filtering burden in a notional dc-fed machine-drive application. Specifically, a set of EMI filter designs is produced to reduce CM emissions below the MIL-STD-461 CE-102 limit: a traditional CM EMI filter, a low-capacitance variant, and a low-inductance variant. The low-capacitance/inductance versions are designed through a model-based approach, in which the antiresonance formed between the ac-side parasitic capacitance of the inverter switch modules and the inductive (machine) load is used to advantage. The antiresonance is employed to notch the worst-offending component of the CM noise source. Thereby the required cutoff frequency of the EMI filter at the input is relaxed and the overall CM filtering burden is significantly reduced.

关键词： Baseplate capacitance conducted EMI leakage current multi-chip power module wide-bandgap

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Modeling and Validation of Conducted Emissions Trends in Medium-Voltage power Electronic Systems 35

Modeling and Validation of Conducted Emissions Trends in Med...

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IEEE Applied power Electronics Conference and Exposition (APEC)

作者： Brovont, Aaron D. Zhao, Jin Lemmon, Andrew N. PC Krause & Associates W Lafayette IN 47906 USA Univ Alabama Dept Elect & Comp Engn Tuscaloosa AL USA

ISBN: (纸本)9781728148298

This paper applies a common-mode modeling approach to a medium-voltage three-level neutral-point-clamped half-bridge inverter within an EMI characterization testbed. A common-mode equivalent model for the system is derived and compared against measured results from a hardware implementation operating over an input range of 1-5 kV. A strong match is observed between analytical prediction and the measured baseplate current in the testbed, which validates the common-mode parasitic model of the inverter. Furthermore, the scaling of common-mode leakage currents with dc-supply voltage is confirmed, establishing the direct tradeoff between efficiency gained through increased voltage and elevated EMI signatures.

关键词： multi-chip power module wide-bandgap common-mode medium voltage neutral-point clamped

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A multi-port thermal coupling model for multi-chip power modules suitable for circuit simulators

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MICROELECTRONICS RELIABILITY 2018年 88-90卷 519-523页

作者： Wang, Z. X. Wang, H. Zhang, Y. Blaabjerg, F. Aalborg Univ Dept Energy Technol Aalborg Denmark

This paper investigates two compact thermal model representations for multi-chip power modules, namely the thermal impedance matrix model and the thermal admittance matrix model. The latter can shape a multi-port thermal network without controlled temperature sources, and can be readily implemented in circuit simulators. The mutual transformation between the two models and their relationship to parameters in the multi-port network are revealed. In addition, practical tips for thermal model parameter extractions based on temperature measurements and curve-fitting are discussed. The multi-port thermal model is verified by simulations and experimental results. It confirms that more accurate temperature estimation can be achieved compared with the thermal model without the thermal coupling effect.

关键词： Thermal model multi-chip power module

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Comparative Evaluation of Kelvin Connection for Current Sharing of multi-chip power modules 10

Comparative Evaluation of Kelvin Connection for Current Shar...

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10th IEEE Annual Energy Conversion Congress and Exposition (ECCE)

作者： Zeng, Zheng Li, Xiaoling Zhang, Xin Cao, Lin Nanyang Technol Univ Sch Elect & Elect Engn Singapore Singapore Chongqing Univ Sch Elect Engn Chongqing Peoples R China CRRC Yongji Elect Co Ltd Xian Shaanxi Peoples R China

ISBN: (纸本)9781479973125

High-capacity power module with multiple parallel chips is a key component for renewable energy applications. Imbalance electro-thermal stresses among the parallel chips challenge the high-capacity power modules. Advanced packaging is considered as a promising solution toward higher capacity of power modules. In this paper, based on a commercial wire-bonding packaging, to enhance the current sharing in the multi-chip insulated-gate bipolar transistor (IGBT) power module, the capability of Kelvin connection to overcome the imbalance transient current and switching loss among parallel chips is comparatively surveyed. Taking parasitics into account, equivalent electric circuit and finite element analysis are proposed to illustrate the influences of Kelvin connection. Based on the customized power modules and a double-pulse test rig, simulation and experimental results are presented to comprehensively demonstrate the current sharing of parallel chips affected by Kelvin connection. It reveals the Kelvin connection can boost switching speed and reduce switching loss. However, the capability to eliminate imbalance current by using Kelvin connection is limited. Optimized direct bonded copper (DBC) layout to eliminate the asymmetric parallel loops is needed for multi-chip modules.

关键词： multi-chip power module transient current sharing Kelvin connection parasitics model

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