multi-chip power module (MCPM) layout design automation has been identified as one of the primary research interests in the power electronics community with the advent of wide bandgap circuits. MCPM physical design re...
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multi-chip power module (MCPM) layout design automation has been identified as one of the primary research interests in the power electronics community with the advent of wide bandgap circuits. MCPM physical design requires a time-consuming iterative procedure that is so far explored manually based on the experience of the designers. Though the number of components and routing layers is limited in power electronics, careful physical design is required because of thermal and reliability issues. In this paper, the benefits of a hierarchical design methodology are demonstrated over the state-of-the-art approaches. We propose a generic, scalable, and efficient algorithm to automate not only 2D but also 2.5D (multiple substrates in a planar package) and 3D (multiple device layers stacked on the same substrate) heterogeneous MCPM layouts considering hierarchy. A complete optimization approach for a full-bridge 2.5D powermodule is demonstrated using hardware-validated electrical and thermal models.
A constraint-aware layout engine is developed for powerSynth to explore heterogeneous powermodule layout synthesis and optimization considering reliability. For this purpose, the corner stitching data structure with ...
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ISBN:
(纸本)9781538659090
A constraint-aware layout engine is developed for powerSynth to explore heterogeneous powermodule layout synthesis and optimization considering reliability. For this purpose, the corner stitching data structure with constraint graph evaluation is extended for powermodule layouts with generic, scalable, and efficient algorithms to place and route heterogeneous components including active devices, sensors, controllers, and other passive components. Unlike VLSI, in powermodules design, layout compaction is not the optimum target because of thermal and reliability issues associated with high voltage and current. Therefore, in this layout engine, both design and reliability constraints are honored while generating layout solutions by evaluating constraint graphs and randomizing edge weights. Compared with existing work, the proposed algorithms can process a broader range of layouts with a higher geometrical complexity within a few minutes. In addition, the produced layouts are both reliable and design-rule-check (DRC)-clean, which improves both time complexity and layout quality.
This paper proposes an improved wire-bonded design with a unique double-end sourced ( DES) structure for multi-chip paralleled silicon carbide (SiC) powermodules. The new structure adopts two pairs of DC bus-bars to ...
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ISBN:
(纸本)9781467395502
This paper proposes an improved wire-bonded design with a unique double-end sourced ( DES) structure for multi-chip paralleled silicon carbide (SiC) powermodules. The new structure adopts two pairs of DC bus-bars to source the powermodule from the two ends, not only shortens the equivalent power loops but also provides a symmetrical structure for the paralleled devices. The proposed design achieved a minimized power-loop inductance of 7.2 nH. In addition, the design improved current sharing among the paralleled devices. A 1200 V, 60 A SiC metal-oxide-semiconductor field-effect-transistor (MOSFET) half-bridge module (3 devices in parallel) is fabricated and tested for verification. Improved performances are observed in both switching and continuous operation. A converter level design is also presented to accommodate this unique module structure.
This paper proposes an improved wire-bonded design with a unique double-end sourced (DES) structure for multi-chip paralleled silicon carbide (SiC) powermodules. The new structure adopts two pairs of DC bus-bars to s...
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ISBN:
(纸本)9781467395519
This paper proposes an improved wire-bonded design with a unique double-end sourced (DES) structure for multi-chip paralleled silicon carbide (SiC) powermodules. The new structure adopts two pairs of DC bus-bars to source the powermodule from the two ends, not only shortens the equivalent power loops but also provides a symmetrical structure for the paralleled devices. The proposed design achieved a minimized power-loop inductance of 7.2 nH. In addition, the design improved current sharing among the paralleled devices. A 1200 V, 60 A SiC metal-oxide-semiconductor field-effect-transistor (MOSFET) half-bridge module (3 devices in parallel) is fabricated and tested for verification. Improved performances are observed in both switching and continuous operation. A converter level design is also presented to accommodate this unique module structure.
Parasitic impedances play a significant role in determining the achievable performance of power electronics applications based on wide band-gap semiconductors. Unlike applications based on traditional devices, this ne...
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ISBN:
(纸本)9781479998838
Parasitic impedances play a significant role in determining the achievable performance of power electronics applications based on wide band-gap semiconductors. Unlike applications based on traditional devices, this new class of applications has spectral content in the "near-RF" domain, which can reveal anomalous system behavior by exciting resonances in these parasitic impedances. To understand and mitigate this behavior, it is important that application designers have some means for estimating the interconnect impedances within multi-chip power modules (MCPM's). This paper proposes a straightforward methodology for extracting estimates of parasitic impedances within the MCPM structure, without a-priori knowledge of the module geometry or interconnection details. The practical utility of the proposed approach is demonstrated through the execution of a case study involving a commercially-available MCPM;and the resulting impedance estimates are empirically validated through switching experiments.
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