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检索条件"主题词=Multi-Memory Architecture"

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A multi-memory Field-Programmable Custom Computing Machine for Accelerating Compute-Intensive Applications 12

A Multi-Memory Field-Programmable Custom Computing Machine f...

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12th IEEE Annual Ubiquitous Computing, Electronics and Mobile Communication Conference (UEMCON)

作者： Jadhav, Shrikant S. Gloster, Clay Naher, Jannatun Doss, Christopher Kim, Youngsoo San Jose State Univ San Jose CA 95192 USA North Carolina A&T State Univ Greensboro NC USA Bradley Univ Peoria IL 61625 USA

ISBN: (纸本)9781665406901

In this paper, we present an FPGA-based multi-memory controller for accelerating computationally intensive applications. Our architecture accepts multiple inputs and produces multiple outputs for each clock cycle. The architecture includes processor cores with pipelined functional units tailored for each application. Additionally, we present an approach to achieve one to two orders-of-magnitude speedup over a traditional software implementation executing on a conventional multi-core processor. Even though the clock frequency of the Field-Programmable Custom Computing Machine (FCCM) is an order-of-magnitude slower than a conventional multi-core processor, the FCCM is significantly faster. We used the Power function as an application to demonstrate the merits of our FCCM. In our experiments, we executed the Power function in software and compared the software execution times with the execution time of an FCCM. Additionally, we also compared FCCM execution time with the OpenMP implementation of the function. Our experiments show that the results obtained using our multi-memory architecture are 57X faster than software implementation and 17X faster than OpenMP implementation executing the Power function, respectively.

关键词： Reconfigurable Computing Field-Programmable Gate Arrays Field-Programmable Custom Computing Machines High Performance Computing multi-memory architecture multiple memory Banks

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An FPGA-based Application-Specific Processor for Implementing the Exponential Function

An FPGA-based Application-Specific Processor for Implementin...

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Annual IEEE SoutheastCon Conference

作者： Jadhav, Shrikant S. Gloster, Clay Naher, Jannatun Doss, Christopher Kim, Youngsoo North Carolina A&T State Univ Dept Comp Syst Technol Greensboro NC 27411 USA North Carolina A&T State Univ Dept Elect & Comp Engn Greensboro NC 27411 USA Bradley Univ Dept Elect Engn Peoria IL 61625 USA

ISBN: (数字)9781728168616

ISBN: (纸本)9781728168616

In this paper, we present a pipelined, high throughput single precision floating point implementation of the exponential function with a latency of 19 cycles. We also present the Application Specific Processor (ASP), a multiple memory architecture that increases memory bandwidth and overall performance of a computationally intensive application. The exponential function hardware unit is used as a function core or arithmetic unit of the ASP. Our experimental results show that executing a hardware implementation of the exponential function on a Field Programmable Gate Array (FPGA) is significantly faster than executing a software implementation on a multi-core processor. While the maximum clock rate of our FPGA board (200 MHz) is an order-of-magnitude slower than our multi-core processor (3.4 GHz), the FPGA-based hardware implementation of the exponential function is 29X and 8X faster than the multi-core processor-based software implementation and OpenMP implementation respectively.

关键词： reconfigurable computing field programmable gate array exponential function multi-memory architecture

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AutoRARE: An Automated Tool For Generating FPGA-Based multi-memory Hardware Accelerators For Compute-Intensive Applications 37

AutoRARE: An Automated Tool For Generating FPGA-Based Multi-...

引用

37th IEEE International Performance Computing and Communications Conference (IPCCC)

作者： Jadhav, Shrikant S. Gloster, Clay Doss, Christopher Kim, Youngsoo Naher, Jannatun North Carolina A&T State Univ Dept Elect & Comp Engn Greensboro NC 27401 USA North Carolina A&T State Univ Dept Comp Syst Technol Greensboro NC USA Bradley Univ Dept Elect & Comp Engn Peoria IL 61625 USA

ISBN: (纸本)9781538668085

In this paper, we present AutoRARE, a Java-based automated design tool for generating Field Programmable Gate Array (FPGA)-based hardware accelerators. AutoRARE automatically generates all VHDL models needed to build/synthesize a processor specifically tailored for each application. The user needs only provide the VHDL description of a special-purpose floating point Arithmetic Logic Unit (ALU) or function core. The tool generates the VHDL description for the memory interface, memory controller, host processor interface, and the application specific processor. We also present details of the FPGA-based multi-memory hardware accelerator for accelerating computationally intensive applications, generated using AutoRARE. The multi-memory hardware accelerator is highly pipelined and able to simultaneously read and write multiple floating point values from multiple memories. The multi-memory architecture is the key to providing hardware accelerators that execute 10X-100X faster than typical multi-core processors. The Taylor Series expansion of the sine/cosine function is used as an application to demonstrate the merits of the multi-memory hardware accelerator. In our experiments, we executed the Taylor Series in software and compared execution times with an FPGA-based hardware implementation. Our experiments show that the FPGA-based multi-memory Taylor Series hardware accelerator is 481X faster than software executing the Taylor Series on a typical server.

关键词： Reconfigurable Computing Field-Programmable Gate Arrays Field-Programmable Custom Computing Machines High Performance Computing multi-memory architecture multiple memory Banks

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AutoRARE: An Automated Tool For Generating FPGA-Based multi-memory Hardware Accelerators For Compute-Intensive Applications

AutoRARE: An Automated Tool For Generating FPGA-Based Multi-...

引用

IEEE International Performance Computing and Communications Conference

作者： Shrikant S. Jadhav Clay Gloster Christopher Doss Youngsoo Kim Jannatun Naher Dept. of Electrical and Computer Engineering North Carolina A&T State University Greensboro NC Dept. of Computer Systems Technology North Carolina A&T State University Greensboro NC Dept. of Electrical and Computer Engineering Bradley University Peoria IL

ISBN: (纸本)9781538668092;9781538668085

关键词： Reconfigurable computing Field-Programmable gate arrays Field-Programmable custom computing machines High performance computing multi-memory architecture multiple memory banks

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