检索结果-内蒙古大学图书馆

GMMSO: game model-combined improved moth search optimization approach for reconfigurable asymmetric multi-processor system-on-chip architecture

引用

ENGINEERING OPTIMIZATION 2023年第4期55卷 685-702页

作者： Mariyappan, Isaivani Veluchamy, Malathi Anna Univ Dept Elect & Elect Engn Reg Campus Madurai Madurai Tamil Nadu India

Heterogeneous multi-processor system-on-chip architectures are prevalent in modern embedded system applications that target high-performance needs. This work comprises two parts to optimize the multiprocessor system structure concerning system speed, power, and area requirements. The first part includes the game model concept, which is remarkably advantageous in generating strategic decisions on incoming signals and minimizes traffic delays coming from the input portion of the system. Secondly, an improved moth search optimization is proposed to explore the design space and optimize the system space and power consumption. This research is implemented in the Field Programmable Gate Array (FPGA) Xilinx Zynq and Virtex platforms and evaluated by ExPRESS benchmarks. The Game Model-combined improved Moth Search Optimization (GMMSO) technique showed performance improvements of 69.34% in delay measurement, 46% in data rate and 36.34% in static power consumption compared with the traditional HMILP (Heuristic Mixed Integer Linear Programming) methods.

关键词： Very large-scale integration multi-processor system-on-chip optimization game model moth search algorithm field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Mcti: mixed-criticality task-based isolation

引用

REAL-TIME systemS 2024年第2期60卷 328-365页

作者： Hoornaert, Denis Ghaemi, Golsana Bastoni, Andrea Mancuso, Renato Caccamo, Marco Corradi, Giulio Tech Univ Munich Chair Cyber Phys Syst Prod Engn Sch Engn & Design Boltzmannstr 15 D-85748 Garching Bavaria Germany Cyber Phys Syst Lab Comp Sci Dept Boston MA USA Xilinx GmbH AMD Co Willy Brandt Allee 4 D-81829 Munich Bavaria Germany

The ever-increasing demand for high performance in the time-critical, low-power embedded domain drives the adoption of powerful but unpredictable, heterogeneous systems-on-chip. On these platforms, the main source of unpredictability-the shared memory subsystem-has been widely studied, and several approaches to mitigate undesired effects have been proposed over the years. Among them, performance-counter-based regulation methods have proved particularly successful. Unfortunately, such regulation methods require precise knowledge of each task's memory consumption and cannot be extended to isolate mixed-criticality tasks running on the same core as the regulation budget is shared. Moreover, the desirable combination of these methodologies with well-known time-isolation techniques-such as server-based reservations-is still an uncharted territory and lacks a precise characterization of possible benefits and limitations. Recognizing the importance of such consolidation for designing predictable real-time systems, we introduce MCTI (Mixed-Criticality Task-based Isolation) as a first initial step in this direction. MCTI is a hardware/software co-design architecture that aims to improve both CPU and memory isolations among tasks with different criticalities even when they share the same CPU. In order to ascertain the correct behavior and distill the benefits of MCTI, we implemented and tested the proposed prototype architecture on a widely available off-the-shelf platform. The evaluation of our prototype shows that (1) MCTI helps shield critical tasks from concurrent non-critical tasks sharing the same memory budget, with only a limited increase in response time being observed, and (2) critical tasks running under memory stress exhibit an average response time close to that achieved when running without memory stress.

关键词： Mixed-criticality Real-time Hardware software co-design multi-processor system-on-chip

来源：评论

学校读者我要写书评

暂无评论

Design Space Exploration of HW Accelerators and Network Infrastructure for FPGA-Based MPSoC

引用

IEEE ACCESS 2024年 12卷 15280-15289页

作者： Dammak, Bouthaina Baklouti, Mouna Alsekait, Deema Princess Nourah Bint Abdulrahman Univ Appl Coll Dept Comp Sci Riyadh 84428 Saudi Arabia Univ Sfax Comp Embedded Syst Lab CES Lab Sfax 3038 Tunisia

Supercomputing systems are increasingly reliant on heterogeneous multiprocessors system on-chip (MPSoCs), merging multiple processors and hardware accelerators (HWAcc) on the same die to achieve power and performance needs. Due to CPU complication and timing closure challenges of tightly coupled design approach, the state-of-the art of HWAcc design methodology relies on coupling the processors with loosely coupled HWAccs. Loosely-coupled HWAccs can be shared or private accelerators running custom instructions to form a heterogeneous multi-processor system. Some works discussed the determination of the sharing degree of the HWAcc over the processors, however the impact of the integrated communication infrastructure is not discussed. Thus, we propose a high-level design exploration tool to select the accelerators and generate the adequate communication interconnect under performance and area constraints. Different homogeneous and heterogeneous multi-processor configurations are evaluated and compared running different signal processing benchmarks. Experimental results show the efficiency of the proposed exploration tool to rapidly explore and select the adequate architecture.

关键词： Program processors Task analysis Computer architecture Field programmable gate arrays Space exploration multiprocessor interconnection Hardware acceleration system-on-chip High level synthesis multi-processor system-on-chip custom instructions shared hardware accelerator network communication high-level exploration

来源：评论

学校读者我要写书评

暂无评论

The Problem of a Symmetric Graph with a Maximum Number of Vertices and Minimum Diameter

引用

LOBACHEVSKII JOURNAL OF MATHEMATICS 2023年第12期44卷 5453-5459页

作者： Sukhov, A. M. Romanov, A. Y. Amerikanov, A. A. Sevastopol State Univ Sevastopol 299053 Russia Natl Res Univ Higher Sch Econ Moscow 123458 Russia

The paper gives a solution for the problem of the topology of the communication subsystem graph for high-performance multi-core computing systems. In this graph, each vertex is connected to four neighbors, and the number of vertices is the maximum for a given graph diameter. The solution to this problem is the family of circulants C(2D(D + 1) + 1;1, 2D + 1), D is diameter. This graph is invariant under transforming its arbitrary vertex into any other, and its vertices are located densely in the vicinity of the root vertex, which determines its compliance with the diameter optimality criterion. All statements formulated during the solution of the problem are proven.

关键词： circulant topology network-on-chip multi-processor system-on-chip computing cluster

来源：评论

学校读者我要写书评

暂无评论

A Survey of MPSoC Management toward Self-Awareness

引用

MICROMACHINES 2024年第5期15卷 577-577页

作者： Gonzalez-Martinez, Guillermo Sandoval-Arechiga, Remberto Solis-Sanchez, Luis Octavio Garcia-Luciano, Laura Ibarra-Delgado, Salvador Solis-Escobedo, Juan Ramon Gomez-Rodriguez, Jose Ricardo Rodriguez-Abdala, Viktor Ivan Univ Autonoma Zacatecas Posgrad Ingn & Tecnol Aplicada PITec Ave Ramon Lopez Velarde 801 Zacatecas 98000 Mexico Univ Autonoma Zacatecas Ctr Invest Innovac & Desarrollo Telecomunicac CIDT Ave Ramon Lopez Velarde 801 Zacatecas 98000 Mexico

Managing multi-processor systems-on-chip (MPSoCs) is becoming increasingly complex as demands for advanced capabilities rise. This complexity is due to the involvement of more processing elements and resources, leading to a higher degree of heterogeneity throughout the system. Over time, management schemes have evolved from simple to autonomous systems with continuous control and monitoring of various parameters such as power distribution, thermal events, fault tolerance, and system security. Autonomous management integrates self-awareness into the system, making it aware of its environment, behavior, and objectives. Self-Aware Cyber-Physical systems-on-chip (SA-CPSoCs) have emerged as a concept to achieve highly autonomous management. Communication infrastructure is also vital to SoCs, and Software-Defined Networks-on-chip (SDNoCs) can serve as a base structure for self-aware systems-on-chip. This paper presents a survey of the evolution of MPSoC management over the last two decades, categorizing research works according to their objectives and improvements. It also discusses the characteristics and properties of SA-CPSoCs and explains why SDNoCs are crucial for these systems.

关键词： multi-processor system-on-chip MPSoC management self-awareness self-aware cyber-physical systems-on-chip software-defined networks-on-chip survey

来源：评论

学校读者我要写书评

暂无评论

CPU-GPU-Memory DVFS for Power-Efficient MPSoC in Mobile Cyber Physical systems

引用

FUTURE INTERNET 2022年第3期14卷 91页

作者： Dey, Somdip Isuwa, Samuel Saha, Suman Singh, Amit Kumar McDonald-Maier, Klaus Univ Essex Sch Comp Sci & Elect Engn CSEE Colchester CO4 3SQ Essex England Nosh Technol Colchester CO4 3SL Essex England Univ Southampton Sch Elect & Comp Sci Southampton SO17 1BJ Hants England

Most modern mobile cyber-physical systems such as smartphones come equipped with multi-processor systems-on-chip (MPSoCs) with variant computing capacity both to cater to performance requirements and reduce power consumption when executing an application. In this paper, we propose a novel approach to dynamic voltage and frequency scaling (DVFS) on CPU, GPU and RAM in a mobile MPSoC, which caters to the performance requirements of the executing application while consuming low power. We evaluate our methodology on a real hardware platform, Odroid XU4, and the experimental results prove the approach to be 26% more power-efficient and 21% more thermal-efficient compared to the state-of-the-art system.

关键词： CPU GPU RAM memory DVFS power consumption multi-processor system-on-chip MPSoC peak temperature thermal behaviour

来源：评论

学校读者我要写书评

暂无评论

A Manycore Vision processor for Real-Time Smart Cameras

引用

SENSORS 2021年第21期21卷 7137-7137页

作者： Silva, Bruno A. da Lima, Arthur M. Arias-Garcia, Janier Huebner, Michael Yudi, Jones Univ Brasilia Automat & Control Grp BR-70910900 Brasilia DF Brazil Fed Univ Minas Gerais UFMG Dept Elect Engn Grad Program Elect Engn BR-31270901 Belo Horizonte MG Brazil Tech Univ Brandenburg Comp Engn D-03046 Brandenburg Germany

Real-time image processing and computer vision systems are now in the mainstream of technologies enabling applications for cyber-physical systems, Internet of Things, augmented reality, and Industry 4.0. These applications bring the need for Smart Cameras for local real-time processing of images and videos. However, the massive amount of data to be processed within short deadlines cannot be handled by most commercial cameras. In this work, we show the design and implementation of a manycore vision processor architecture to be used in Smart Cameras. With massive parallelism exploration and application-specific characteristics, our architecture is composed of distributed processing elements and memories connected through a Network-on-chip. The architecture was implemented as an FPGA overlay, focusing on optimized hardware utilization. The parameterized architecture was characterized by its hardware occupation, maximum operating frequency, and processing frame rate. Different configurations ranging from one to eighty-one processing elements were implemented and compared to several works from the literature. Using a system-on-chip composed of an FPGA integrated into a general-purpose processor, we showcase the flexibility and efficiency of the hardware/software architecture. The results show that the proposed architecture successfully allies programmability and performance, being a suitable alternative for future Smart Cameras.

关键词： multi-processor system-on-chip network-on-chip image processing computer vision real-time smart camera

来源：评论

学校读者我要写书评

暂无评论

Static Data-Flow Analysis of UML/SysML Functional Views for Signal and Image Processing Applications 1

引用

7th International Conference on Model-Driven Engineering and Software Development (MODELSWARD)

作者： Enrici, Andrea Apvrille, Ludovic Pacalet, Renaud Pham, Minh Hiep Nokia Bell Labs F-91620 Nozay France Inst Polytech Paris LTCI Telecom Paris F-75013 Paris France

ISBN: (数字)9783030378738

ISBN: (纸本)9783030378738;9783030378721

The complexity of heterogeneous multi-processor systems-on-chip stretches the limits of software development solutions based on sequential languages such as C/C++. While these are still the most widely used languages in practice, model-based solutions appear to be an efficient alternative. However, the optimized compilation of models for multi-processor systems still presents many open research problems. Among others, static data-flow analyses for models require the adaptation of traditional algorithms used in program analysis (iterative and worklist algorithms). These algorithms operate on Control-Flow Graphs with a unique start node (i.e., a node without predecessors) and assume that every basic block is reachable from this start node. In this paper, we present a novel combination of the well-known iterative and worklist algorithms that examines a Control-Flow Graph where basic blocks can be reached by paths that originate from different start states. We apply this solution to functional views of signal and image processing models denoted with UML Activity and SysML Block diagrams. We demonstrate its effectiveness on interval analysis and show that significant reductions in the number of visits of the models' control-flow graphs can be achieved.

关键词： Static data-flow analysis Optimizing model compilation UML/SysML multi-processor system-on-chip

来源：评论

学校读者我要写书评

暂无评论

A new approach to the Population-Based Incremental Learning algorithm using virtual regions for task mapping on NoCs

引用

JOURNAL OF systemS ARCHITECTURE 2019年 97卷 443-454页

作者： Garcia Morales, L. G. Aedo Cobo, J. E. Bagherzadeh, N. Univ Antioquia Dept Elect Engn Medellin Colombia Univ Calif Irvine Dept Elect Engn & Comp Sci Comp Engn Irvine CA USA

Network-On-chip (NoC) platforms were proposed to increase system performance in current and future generations of multi-processor system-on-chip ranging from a few cores to hundreds. For such platforms, efficient mechanisms to perform the mapping of executable tasks are required in order to improve metrics such as execution time, latency, energy, and others. The Population-Based Incremental Learning (PBIL) algorithm has been used as an optimization technique for the mapping of tasks onto the cores of NoC platforms. However, it does not scale well in terms of latency and other relevant metrics when the size of the platform and the number of tasks are increased. In this work, we propose a new approach, that relies on the PBIL algorithm, for the mapping of tasks called Virtual Regions PBIL (VRPBIL-NoC). This strategy consists of dividing the platform into virtual regions in order to improve the search of quality solutions. We evaluate the performance of our technique by comparing it against a set of heuristic techniques available in the literature, using an extended version of a well-known state-of-the-art simulator called Noxim. The results demonstrated that our approach can deliver better solutions compared to those provided by the other techniques in NoCs for varied configurations.

关键词： Network-on-chip multi-Applications multi-processor system-on-chip Population-Based Incremental Learning Task mapping

来源：评论

学校读者我要写书评

暂无评论

NoC Performance Estimation Based on Queueing Theory for Real Scientific Applications

NoC Performance Estimation Based on Queueing Theory for Real...

引用

IEEE International Conference on Mechatronics, Electronics and Automotive Engineering (ICMEAE)

作者： Piedrahita-Velasquez, Carlos A. Patino, Gustavo Duque, Juan Pablo Urrea Univ Antioquia SISTEMIC Grp Medellin Colombia Univ Antioquia GITA Grp Medellin Colombia

ISBN: (纸本)9781728160375

The estimation of performance metrics of a Network-on-chip (NoC) is an increasingly important aspect of multiprocessor system-on-chip (MPSoC) design. As systems grow in number of components and features, the correct design of the Network-on-chip has a central role in meeting the performance requirements of the system, because it is responsible for the efficient movement of data inside the MPSoC. In this paper a software tool called NoCSimulator which is based in queueing theory for the estimation of latency and throughput of a NoC is proposed. The contribution of this tool is its ability to generate stochastic traffic patterns based on real data traffic of scientific applications, not only synthetic traffic as similar tools reported in literature. This makes it possible to study NoC performance under real working conditions, which gives better insights about NoC behavior, and improves the design space exploration at early stages of system development. NoCSimulator was validated using two state-of-the-art cycle-accurate simulators (BookSim and Garnet). NoCSimulator, based in queueing theory, does not model hardware aspects of the NoC as a cycle-accurate simulator, so, long simulation times of complex systems can be avoided during design space exploration.

关键词： multi-processor system-on-chip Network-on-chip latency throughput queueing theory cycle-accurate simulation

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：