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PARAMINER: a generic pattern mining algorithm for multi-core architectures

DATA MINING AND KNOWLEDGE DISCOVERY 2014年第3期28卷 593-633页

作者： Negrevergne, Benjamin Termier, Alexandre Rousset, Marie-Christine Mehaut, Jean-Francois Univ Grenoble LIG Lab Grenoble France

In this paper, we present Para Miner which is a generic and parallel algorithm for closed pattern mining. Para Miner is built on the principles of pattern enumeration in strongly accessible set systems. Its efficiency is due to a novel dataset reduction technique (that we call EL-reduction), combined with novel technique for performing dataset reduction in a parallel execution on a multi-core architecture. We illustrate Para Miner's genericity by using this algorithm to solve three different pattern mining problems: the frequent itemset mining problem, the mining frequent connected relational graphs problem and the mining gradual itemsets problem. In this paper, we prove the soundness and the completeness of Para Miner. Furthermore, our experiments show that despite being a generic algorithm, Para Miner can compete with specialized state of the art algorithms designed for the pattern mining problems mentioned above. Besides, for the particular problem of gradual itemset mining, Para Miner outperforms the state of the art algorithm by two orders of magnitude.

关键词： Data mining Closed pattern mining Parallel pattern mining multi-core architectures

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BRAM-based function reuse for multi-core architectures in FPGAs

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MICROPROCESSORS AND MICROSYSTEMS 2018年 63卷 237-248页

作者： Exenberger Becker, Pedro H. Sartor, Anderson L. Brandalero, Marcelo Schneider Beck, Antonio C. Univ Fed Rio Grande do Sul Inst Informat BR-91501970 Porto Alegre RS Brazil

Modern processors contain several specific hardware modules and multiple cores to ensure performance for a wide range of applications. In this context, FPGAs are frequently used as the implementation platform, since they offer architecture customization and fast time-to-market. However, many of them may not have the needed resources to implement all the necessary features, because of costs or complexity of the system to be implemented. When some needed functionalities do not fit in the target, they must be mapped into the much slower software domain. In this work, we exploit the fact these designs usually underuse their available BRAMs and propose a low-cost hardware-based function reuse mechanism for FPGAs, recovering some of the performance lost from the software part of applications that could not be implemented in hardware logic, with minimal impact on LUT usage. This is achieved by saving the inputs and outputs of the most frequently executed functions in a BRAM-based reuse table, so the next function executions with the same arguments can be skipped. This mechanism supports both precise and approximate modes and is evaluated with a 4-issue VLIW processor implemented in HDL, also considering a multi-core environment. Precise reuse, in single and multi-core scenarios, is assessed by running applications that use a software library to emulate floating point operations. Approximate reuse is evaluated over a single-core image-processing application that tolerates a certain level of error. Our scheme achieves 1.39 x geomean speedup in the precise single-core, while the multi-core case demonstrates application improvements from 1.25 x to 1.9 x when we start sharing the reuse table. In the approximate scenario, we achieve 1.52 x speedup with less than 10% error. (C) 2018 Elsevier B.V. All rights reserved.

关键词： Function-reuse Soft-processors multi-core architectures FPGA

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Performance issues in emerging homogeneous multi-core architectures

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SIMULATION MODELLING PRACTICE AND THEORY 2009年第9期17卷 1485-1499页

作者： Kayi, Abdullah El-Ghazawi, Tarek Newby, Gregory B. George Washington Univ Dept Elect & Comp Engn Washington DC 20052 USA Arctic Reg Supercomp Ctr Fairbanks AK 99775 USA

multi-core architectures have emerged as the dominant architecture for both desktop and high-performance systems. multi-core systems introduce many challenges that need to be addressed to achieve the best performance. Therefore, benchmarking of these processors is necessary to identify the possible performance issues. In this paper, broad range of homogeneous multi-core architectures are investigated in terms of essential performance metrics. To measure performance. we used micro-benchmarks from High-Performance Computing Challenge (HPCC), NAS Parallel Benchmarks (NPB), LMbench, and an FFT benchmark. Performance analysis is conducted on multi-core systems from UltraSPARC and x86 architectures;including systems based on Conroe, Kentsfield, Clovertown, Santa Rosa, Barcelona, Niagara, and Victoria Falls processors. Also, the effect of multi-core architectures in cluster performance is examined using a Clovertown based cluster. Finally, cache coherence overhead is analyzed using a full-system Simulator. Experimental analysis and observations in this study provide for a better understanding of the emerging homogeneous multi-core systems. (C) 2009 Elsevier B.V. All rights reserved.

关键词： multi-core architectures Micro-benchmarking Performance analysis Coherence misses Full-system simulation

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ParIS plus : Data Series Indexing on multi-core architectures

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IEEE TRANSACTIONS ON KNOWLEDGE AND DATA ENGINEERING 2021年第5期33卷 2151-2164页

作者： Peng, Botao Fatourou, Panagiota Palpanas, Themis Univ Paris LIPADE F-75006 Paris France FORTH ICS Iraklion Greece Univ Crete Dept Comp Sci Iraklion 70013 Greece

Data series similarity search is a core operation for several data series analysis applications across many different domains. Nevertheless, even state-of-the-art techniques cannot provide the time performance required for large data series collections. We propose ParIS and ParIS+, the first disk-based data series indices carefully designed to inherently take advantage of multi-core architectures, in order to accelerate similarity search processing times. Our experiments demonstrate that ParIS+ completely removes the CPU latency during index construction for disk-resident data, and for exact query answering is up to 1 order of magnitude faster than the current state of the art index scan method, and up to 3 orders of magnitude faster than the optimized serial scan method. ParIS+ (which is an evolution of the ADS+ index) owes its efficiency to the effective use of multi-core and multi-socket architectures, in order to distribute and execute in parallel both index construction and query answering, and to the exploitation of the Single Instruction multiple Data (SIMD) capabilities of modern CPUs, in order to further parallelize the execution of instructions inside each core.

关键词： Indexing Task analysis Parallel processing Hardware Aggregates multicore processing Data series time series indexing similarity search query answering multi-core architectures parallelization

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Analyzing large-scale DNA Sequences on multi-core architectures 18

Analyzing large-scale DNA Sequences on Multi-core Architectu...

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18th IEEE International Conference on Computational Science and Engineering (CSE)

作者： Memeti, Suejb Pllana, Sabri Linnaeus Univ Dept Comp Sci S-35195 Vaxjo Sweden

ISBN: (纸本)9781467382977

Rapid analysis of DNA sequences is important in preventing the evolution of different viruses and bacteria during an early phase, early diagnosis of genetic predispositions to certain diseases (cancer, cardiovascular diseases), and in DNA forensics. However, real-world DNA sequences may comprise several Gigabytes and the process of DNA analysis demands adequate computational resources to be completed within a reasonable time. In this paper we present a scalable approach for parallel DNA analysis that is based on Finite Automata, and which is suitable for analyzing very large DNA segments. We evaluate our approach for real-world DNA segments of mouse (2.7GB), cat (2.4GB), dog (2.4GB), chicken (1GB), human (3.2GB) and turkey (0.2GB). Experimental results on a dual-socket shared-memory system with 24 physical cores show speedups of up to 17.6x. Our approach is up to 3x faster than a pattern-based parallel approach that uses the RE2 library.

关键词： parallel DNA analysis multi-core architectures finite automata

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A bridging model for branch-and-bound algorithms on multi-core architectures

A bridging model for branch-and-bound algorithms on multi-co...

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5th International Symposium on Parallel architectures, Algorithms and Programming (PAAP)

作者： Savadi, Abdorreza Deldari, Hossein Ferdowsi Univ Mashhad Dept Comp Engn Mashhad Iran Islamic Azad Univ Mashhad Branch IAUM Dept Comp Engn Mashhad Iran

ISBN: (纸本)9780769548982;9781467345668

Nowadays, the evolution of multi-core architectures goes towards increasing the number of cores and levels of cache. Meanwhile, current typical parallel programming languages are unable to exploit the potential of these processors efficiently. In order to achieve desired performance on these hardwares we need to understand architectural parameters appropriately and also apply them in algorithm design. Computational models such as multi-BSP, illustrate these parameters and explain adequate methods for designing algorithms on multi-cores. One of applicable categories of problems is Branch-and-Bound (BaB) that needs to be adapted by such model for implementing on these systems. In this paper, we have attempted to make a mapping between BaB run-time tree and the Memory Hierarchy Tree (MT) of multi-core processor. multi-BSP model inspired us to introduce multi-BaB model. Analogous to multi-BSP analysis, bounds for communication and synchronization costs have been presented in the paper respecting BaB algorithms. This work is a step towards making multi-core programming efficient and tries to obtain correct analysis of BaB algorithm behavior on multi-core architectures.

关键词： multi-BSP Branch-and-Bound(BaB) Parallel Model multi-core architectures Cache Memory Hierarchy

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multiCUBE: multi-Objective Design Space Exploration of multi-core architectures

MULTICUBE: Multi-Objective Design Space Exploration of Multi...

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IEEE Annual Symposium on VLSI (ISVLSI)

作者： Silvano, Cristina Fornaciari, William Palermo, Gianluca Zaccaria, Vittorio Castro, Fabrizio Martinez, Marcos Bocchio, Sara Zafalon, Roberto Avasare, Prabhat Vanmeerbeeck, Geert Ykman-Couvreur, Chantal Wouters, Maryse Kavka, Carlos Onesti, Luka Turco, Alessandro Bondi, Umberto Mariani, Giovanni Posadas, Hector Villar, Eugenio Wu, Chris Fan Dongrui Hao, Zhang Tang Shibin Politecn Milan Dipartimento Elettron Informaz Milan Italy Design Syst Silicon DS2 Valencia Spain TSTMicroelect Cornaredo Italy IMEC VZW Leuven Belgium ESTECO Trieste Italy Univ Svizzera Italiana ALaRI Lugano Switzerland Univ Cantabria Cantabria Spain STMicroelect Beijing Peoples R China Chinese Acad Sci Inst Comp Technol Beijing Peoples R China

ISBN: (纸本)9780769540764

Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the multiCUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures(1).

关键词： Design Space Exploration multiCUBE multi-core architectures logic design multicore architecture multiobjective design space exploration multiprocessing systems parallel architectures parallel embedded architecture system-on-chip system-on-chip

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Fast and Scalable Thread Migration for multi-core architectures 13

Fast and Scalable Thread Migration for Multi-Core Architectu...

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13th International Conference on Embedded and Ubiquitous Computing (EUC 2015)

作者： Rodrigues, Miguel Roma, Nuno Tomas, Pedro Univ Lisbon Inst Super Tecn INESC ID Lisbon Portugal

ISBN: (纸本)9781467382991

Heterogeneous computing is a promising approach to tackle the thermal, power and energy constraints posed by modern desktop and embedded computing systems. However, by also allowing the migration of application threads to the most appropriate cores, significant performance gains and energy efficiency levels can also be attained. Nevertheless, the considerably large overheads usually imposed by software-based thread migration procedures only allow exploiting migrations at a coarse-grained level, thus limiting the effectiveness of using such techniques. Accordingly, this paper proposes a fast and efficient hardware-based thread migration mechanism that can be easily plugged-in into any core architecture. To minimize the thread migration overhead and latency, the proposed approach considers both soft-and hard-migration procedures, and adopts a conventional "most recently used" prediction scheme to identify the cache blocks that should be migrated along with the thread context. Experimental results show that the proposed scheme is lightweight and requires limited hardware resources, while allowing to attain migration latencies below 100 clock cycles and to reduce post-migration overheads in up to 60%, making it particularly appropriate for exploiting short-lived application phases.

关键词： multi-core architectures Parallel Processing Thread Migration PARALLEL PROCESSING (COMPUTERS) core construction THREADS Migrations Program Thread Immigration Fasting hardware resource clock cycle Thermal power Cache memory Lightweight

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Buffer-space Efficient and Deadlock-free Scheduling of Stream Applications on multi-core architectures 10

Buffer-space Efficient and Deadlock-free Scheduling of Strea...

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22nd ACM Symposium on Parallelism in Algorithms and architectures

作者： Park, Jongsoo Dally, William J. Stanford Univ Comp Syst Lab Stanford CA 94305 USA

ISBN: (纸本)9781450300797

We present a scheduling algorithm of stream programs for multi-core architectures called team scheduling Compared to previous multi-core stream scheduling algorithms, team scheduling achieves 1) similar synchronization overhead, 2) coverage of a larger class of applications, 3) better control over buffer space, 4) deadlock-free feedback loops, and 5) lower latency We compare team scheduling to the latest stream scheduling algorithm, SGMS, by evaluating 14 applications on a multi-core architecture with 16 cores. Team scheduling successfully targets applications that cannot be validly scheduled by SGMS clue to excessive buffer requirement or deadlocks in feedback loops (e.g., GSM and W-cDmA) For applications that can be validly scheduled by SGMS, team scheduling shows on average 37% higher throughput within the same buffer space constraints

关键词： Compiler and Tools for Concurrent Programming Stream Programming Green Computing and Power-Efficient architectures multi-core architectures

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Design and Development of a Run-Time Monitor for multi-core architectures in Cloud Computing

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SENSORS 2011年第4期11卷 3595-3610页

作者： Kang, Mikyung Kang, Dong-In Crago, Stephen P. Park, Gyung-Leen Lee, Junghoon Jeju Natl Univ Dept Comp Sci & Stat Cheju 690756 South Korea Univ So Calif Inst Informat Sci Arlington VA 22203 USA

Cloud computing is a new information technology trend that moves computing and data away from desktops and portable PCs into large data centers. The basic principle of cloud computing is to deliver applications as services over the Internet as well as infrastructure. A cloud is a type of parallel and distributed system consisting of a collection of inter-connected and virtualized computers that are dynamically provisioned and presented as one or more unified computing resources. The large-scale distributed applications on a cloud require adaptive service-based software, which has the capability of monitoring system status changes, analyzing the monitored information, and adapting its service configuration while considering tradeoffs among multiple QoS features simultaneously. In this paper, we design and develop a Run-Time Monitor (RTM) which is a system software to monitor the application behavior at run-time, analyze the collected information, and optimize cloud computing resources for multi-core architectures. RTM monitors application software through library instrumentation as well as underlying hardware through a performance counter optimizing its computing configuration based on the analyzed data.

关键词： Run-Time Monitor multi-core architectures cloud computing QoS library instrumentation performance counter

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