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A Practical Cache Partitioning Method for multi-core processor on a Commercial Safety-Critical Partitioned RTOS

IEEE ACCESS 2025年 13卷 25505-25519页

作者： Kim, Taeho Seoul Womens Univ Informat Secur Div Seoul 01797 South Korea

In modern airborne systems, software plays a crucial role for meeting functional, safety, and performance requirements. Integrated Modular Avionics (IMA) and multi-core processors (MCPs) are also adopted for hardware to enhance performance and Space, Weight, and Power (SWaP). While MCPs improve efficiency, they introduce nondeterministic behaviors due to resource contention and challenges for the safety of avionics systems. This research proposes a practical cache partitioning method for commercial Real-Time Operating Systems (RTOS) on MCPs to reduce cache contention and enhance the safety and performance of avionics systems. A systematic procedure was developed based on DO-178 and CAST 32A to identify shared resources and prevent interference. Additionally, we developed a cache partitioning guide tool to decide the optimal cache partition for each application. This research demonstrated that shared L2 caches could cause severe performance degradation up to 88% using the WindRiver VxWorks 653 on the PowerPC T2080 processor. By applying the proposed partitioning technique, the system achieved 0% performance degradation, eliminating cache contention and ensuring consistent application performance. The partitioning approach also ensured deterministic application behavior, a critical requirement for safety-critical systems. Validation in a flight simulation environment confirmed the practicality of the method in real-world scenarios.

关键词： Aerospace electronics Software Operating systems Interference Safety multicore processing Hardware Object recognition Real-time systems Computer architecture Avionics real-time operating systems cache partitioning safety-critical systems multi-core processor

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S2MSim: Cycle-Accurate and High-Performance Simulator Based on multi-Threading for Space multi-core processor

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INTERNATIONAL JOURNAL OF AERONAUTICAL AND SPACE SCIENCES 2023年第5期24卷 1465-1478页

作者： Jeong, Jae-Yeop Lee, Cheol-Hoon Korea Aerosp Res Inst Satellite Technol Res & Dev Div 169-84 Gwahak Ro Daejeon 34133 South Korea Chungnam Natl Univ Dept Comp Sci & Engn 99 Daehak Ro Daejeon 34134 South Korea

A processor simulator is an essential tool for developing, testing, and verifying flight software in the space domain;this tool should be capable of correctly simulating a space-grade processor with high performance and cycle-accuracy. Existing space simulators typically use single-thread-based interpretation methods to satisfy these requirements. Since these methods involve sequential core execution by a single thread, which degrades the overall performance and cycle-accuracy, they are unsuitable for multi-core processor simulations. In this study, we propose a cycle-accurate and high-performance multi-core processor simulator based on multi-threading called the Scalable processor Architecture multi-core multi-threading simulator (S2MSim) which accurately models the working of the GR740 quad-core processor through three schemes. First, we assigned each GR740 core to a host thread to improve the performance and dynamically allocated a simulator manager to these specific host threads to minimize the overhead induced by thread communications. Second, we analyzed the inter-core interference effects and reflected the results required for each core to achieve a high cycle-accuracy. Finally, we used a fine-grained lock to provide the simulated cores with simultaneous access to shared resources and spin-lock to thread synchronization. The experimental results showed that on an average, the S2MSim could run 3.09 and 4.18 times faster than TSIM3-LEON4 and laysim-gr740, respectively. We achieved a high cycle-accuracy within a +/- 3% error margin compared to that shown by the GR740 development board from Cobham Gaisler AB.

关键词： GR740 Parallel simulator Flight software multi-core processor Cycle-accuracy

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Using Terahertz On-Chip Antennas for Intra-Chip Wireless Communications within a multi-core processor 49

Using Terahertz On-Chip Antennas for Intra-Chip Wireless Com...

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49th International Conference on Infrared, Millimeter, and Terahertz Waves (IRMMW-THz)

作者： Paudel, Biswash Li, Xue Jun Seet, Boon-Chong Auckland Univ Technol Dept EEE Auckland New Zealand

ISBN: (纸本)9798350370331;9798350370324

This paper explores the integration of terahertz (THz) on-chip antennas onto System-on-Chip (SoC) platforms for high-performance computing. Simulation studies were conducted to analyze transmission characteristics and electrical-field distribution, indicating the potential application of THz on-chip antennas for intra-chip communications within multi-core processor, providing higher signal bandwidth to enhance their computational capability through micron-sized THz dipole antennas.

关键词： THzWiNoC on-chip antenna flip-chip package multi-core processor

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Research on optimization of stream data processing algorithm for multi-core processor based on MapReduce 7

Research on optimization of stream data processing algorithm...

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7th International Conference on Automation Electronics and Electrical Engineering

作者： Shang, Yingmei Wang, Genjie Ruan, Jing Anhui Sanlian Univ Hefei Anhui Peoples R China

ISBN: (纸本)9798350377040;9798350377033

With the rapid development of information technology and the popularization of the Internet, streaming data processing has become one of the core tasks of big data analysis. With their parallel computing capabilities, multi-core processors show great potential in efficiently processing massive streams of data. However, the traditional streaming data processing algorithm often faces the problems of uneven resource allocation, unbalanced load and high communication overhead when facing multi-core architecture, which limits the overall performance of the system. Based on MapReduce programming model, this paper discusses the optimization strategy of streaming data processing algorithm in multi-core processor environment. Firstly, this paper analyzes the limitations of the existing MapReduce framework in the stream data processing scenario, including the delay increase caused by batch processing tendency and the lack of adaptability to dynamic data flow. Then, an improved Partitioning Strategy is proposed, which can dynamically adjust task allocation according to data flow characteristics, ensure load balancing among cores, and minimize cross-core communication costs. In order to further improve the processing efficiency, this paper also designs a kernel processor stream data processing algorithm based on MapReduce-partitioning strategy, which can dynamically adjust the task priority and optimize the execution order according to real-time performance monitoring information. The experimental results show that the proposed optimization method not only effectively improves the speed of upstream data processing, but also enhances the stability and reliability of the system, which provides theoretical support and technical reference for future large-scale streaming data analysis.

关键词： multi-core processor MapReduce load balancing partition strategy

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Near-Infrared Off-Axis integrated cavity output spectroscopic sensor system for ammonia leakage measurement in cold store using embedded multi-core processor

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INFRARED PHYSICS & TECHNOLOGY 2024年 137卷

作者： Hua, Ying Zhang, Lei Zhou, Yishen Yu, Ling Zheng, Kaiyuan Song, Fang Liu, Mingshi Yang, Yue Zheng, Chuantao Wang, Yiding Jilin Univ Coll Elect Sci & Engn State Key Lab Integrated Optoelect 2699 Qianjin St Changchun 130012 Peoples R China Hong Kong Polytech Univ Photon Res Inst Dept Elect Engn Hong Kong 518060 Peoples R China Shandong Technol & Business Univ Sch Comp Sci & Technol Yantai 264005 Peoples R China

A near-infrared off-axis integrated cavity output spectroscopic (OA-ICOS) sensor system for ammonia (NH3) leakage detection was developed. A distributed feedback (DFB) laser was used to target the absorption line of NH3 at 6612.167 cm-1. Experiments were conducted to evaluate the performance of the sensor system. When the averaging time is 0.8 s, the detection limit (1 sigma) of NH3 is - 1.21 parts-per-million by volume (ppmv) using wavelength modulation spectroscopy (WMS). The 10-90 % response time of the NH3 sensor system is - 7.2 s. Based on the developed local monitoring and control platform (LMCP), cloud server, remote monitoring and control end (RMCE), the unattended NH3 leakage detection experiments were carried out in a cold store located in Jilin City. The experimental results confirmed the rapid detection capability of the reported sensor system for NH3 leakage as well as the capability of remote monitoring and control.

关键词： Infrared absorption ammonia (NH 3 ) leakage detection OA-ICOS multi-core processor multithreading technology Sensor networking

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Development of personalized mobile information service platform of university library based on multi-core processor and cloud computing platform

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SOFT COMPUTING 2023年

作者： Li, Yingxin Shandong Univ Lib Jinan 250100 Shandong Peoples R China

In recent years, depending on information technology, knowledge and skills, university libraries have established a new "user-centered" data service system, which is called personalized information service. Although this service has made some progress in recent years, these systems have only achieved a certain amount of personalized information services. multi-core processor is the basic process unit of high-performance cloud computing node, which is an important basis to achieve system security, high-performance, low-power consumption and other high-performance requirements. Cloud computing node is one of the core components in the high-performance computer system architecture, in addition to the acceleration node, master control unit, communication system, etc., its efficiency has constituted an important basic condition for the realization of the "high efficiency" goal of the system. The emergence of multi-core processors and cloud computing platforms has created conditions for the development of personalized mobile information service platforms in university libraries. Under the technical support of multi-core processors and cloud computing platforms, it is also an important goal of mobile libraries in the future to meet the needs of users to search library data information at any time and provide users with diversified data services. At present, the knowledge service platform of university library can not only actively select and recommend relevant materials for users according to their knowledge preferences, data utilization habits and academic backgrounds, but also enable service users to quickly obtain the borrowing expiration prompt, independent consultation and retrieval and other personalized information functions, and carry out more in-depth personalized intelligent knowledge consulting services. Based on multi-core processor and cloud computing platform, this paper develops personalized mobile information service platform of university library.

关键词： multi-core processor Cloud computing platform University library Platform development

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multi-core processor partitioned task scheduling algorithm design based on ARINC653 21

Multi-core processor partitioned task scheduling algorithm d...

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Proceedings of the 2021 4th International Conference on E-Business, Information Management and Computer Science

作者： Ming Li Suyang Wei Wentao Sun He Zhang CETC Avionics CO. LTD China University of Electronic Science and Technology of China China

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A Study on the Implementation of Vector Control System Using the Model Base Parallelization Tool on multi-core processor 23

A Study on the Implementation of Vector Control System Using...

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23rd International Conference on Electrical Machines and Systems (ICEMS)

作者： Kim, Jinsoo Kato, Seiya Honda, Shinya Edahiro, Masato Doki, Shinji Nagoya Univ Chikusa Ku Furo Cho Nagoya Aichi 4648601 Japan Nanzan Univ Showa Ku Yamazato Cho Nagoya Aichi 4668673 Japan

ISBN: (纸本)9784886864192

The scope of embedded systems used by multicore processors is widely applied to various products that require control, such as home appliances, industrial devices, transportation devices, and communication terminals. Model-Base Parallelization technology was proposed towards efficient parallelization to implement a control system in the introduction of multi-core processors. By applying MBP, it is possible to parallelization even details that people are not aware of, but the control system with numerous causal relationships still does not sufficiently utilize multi-core. Therefore, a method of inserting a time-delay is being studied as a method for improving the parallelization of multi-cores. In this paper, We describe the insertion location that improves parallelization and does not affect the control performance by inserting time-delay to implement the vector control system of PMSM on multi-core efficiently.

关键词： PMSM multi-core processor Parallelization Time-Delay Vector Control

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Learning-based BTI stress estimation and mitigation in multi-core processor systems

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MICROprocessorS AND MICROSYSTEMS 2021年 81卷 103713-103713页

作者： Abbas, Haider Muhi Halak, Basel Zwolinski, Mark Univ Technol Baghdad Baghdad Iraq Univ Southampton Southampton Hants England

With the increasing demand of designing a reliable processing devices, the issue of CMOS ageing is jeopardising the industry of digital devices. Many studies has been cover this area for modelling the ageing behaviour at the device level or developing ageing sensors for on-line delay detection at the system level. However, we are presenting a method to estimate the ageing stresses (e.g. Temperature, Ageing Stress Activity) rather than the modelling ageing (performance degradation) itself. The purpose for estimating the ageing stress is to optimise the system utilisation with the minimisation of ageing stress. In multicore processors, the existence of more than one source of ageing stress is higher than single core processor but the optimisation space is higher as well along with the temperature and power optimisation. In this paper, we have modelled the ageing stress from the application level using machine learning techniques to train data extracted from high level workloads ( e.g. parsec and splash2 benchmarks) on four cores processor from Xeon. The ageing stress model is able to estimate the ageing stress with 0.1% error and is able to proactively reduce the ageing stress by 50%.

关键词： Bias temperature instability (BTI) Ageing stress multi-core processor Proactive solution Neural network

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An Efficient Mining Algorithm of Closed Frequent Itemsets on multi-core processor 15th

An Efficient Mining Algorithm of Closed Frequent Itemsets on...

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15th International Conference on Advanced Data Mining and Applications (ADMA)

作者： Phan, Huan Univ Social Sci & Humanities VNU HCMC Div IT Ho Chi Minh City Vietnam Univ Sci VNU HCMC Fac Math & Comp Sci Ho Chi Minh City Vietnam

ISBN: (纸本)9783030352318;9783030352301

In this paper, we improved a sequential NOV-CFI algorithm mining closed frequent itemsets in transaction databases, called SEQ-CFI and consisting of three phases: the first phase, quickly detect a Kernel_COOC array of co-occurrences and occurrences of kernel item in at least one transaction;the second phase, we built the list of nLOOC-Tree base on the Kernel_COOC and a binary matrix of dataset (self-reduced search space);the last phase, the algorithm is a fast mining closed frequent itemsets base on nLOOC-Tree. The next step, we develop a sequential algorithm for mining closed frequent itemsets and thus parallelize the sequential algorithm to effectively demonstrate the multi-core processor, called NPA-CFI. The experimental results show that the proposed algorithms perform better than other existing algorithms, as well as to expand the parallel NPA-CFI algorithm on distributed computing systems such as Hadoop, Spark.

关键词： Co-occurrence items Closed frequent itemsets multi-core processor Parallel NPA-CFI algorithm

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