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检索条件"主题词=Multi-core system"

共 60 条记录，以下是1-10 订阅

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Design of a Data Transmission Control Unit in a multi-core DSP system 15

Design of a Data Transmission Control Unit in a Multi-core D...

引用

15th IEEE International Conference on ASIC, ASICON 2023

作者： Ge, Hu Yuan, Qiao Zhang, Yuhao Song, Yukun Li, Zhenmin School of Microelectronics Hefei University of Technology Hefei China Space Star Technology Co. Ltd Beijing China

ISBN: (纸本)9798350312980

With the development of multi-core DSP system, the paradigm of parallel processing is widely used, and the data transmission rate has been greatly improved. The traditional inter-core communication and data transmission between cores and peripherals have an inefficient way of data transmission, which limits the performance of scheduling and congestion control of data transmission tasks, and therefore no longer meet the growing system requirements. This paper focuses on a data transmission control unit applied to data transmission management in DSP multi-core systems. In the face of multi-device transmission requests, a distributed data transmission control unit is used to mobilize multiple DMA units to work in parallel to achieve efficient transmission of data transmission tasks in multi-core DSP systems. The experimental results prove that compared with the traditional task management method, the proposed data transmission control unit improves the task response efficiency notably, reduces the task response time, and improves the overall system performance. © 2023 IEEE.

关键词： data transmission control DSP multi-core system

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ROS Task Scheduling Algorithm in multi-core system 25

ROS Task Scheduling Algorithm in Multi-Core System

引用

25th IEEE International Conference on Parallel and Distributed systems (IEEE ICPADS)

作者： Ding, Nan Meng, Xianghua Zhao, Yawen Wu, Di Dalian Univ Technol Coll Comp Sci & Technol Dalian Peoples R China Dalian Univ Technol Coll Control Sci & Engn Dalian Peoples R China

ISBN: (纸本)9781728125831

This paper designs a task scheduling algorithm called RTSA (ROS Task Scheduling Algorithm) for Linux kernel in allusion to the inherent relevance and mapping relationship of ROS under the development framework of ROS and Linux, considering multiple factors such as multi-core load, task computational overhead, communication overhead. This paper uses simulation to verify the correctness of RTSA, and compares RTSA with the Round-Robin Scheduling algorithm, SSC algorithm and serial execution. It turns out that RTSA can effectively shorten task scheduling length, reduce communication overhead, and improve system performance.

关键词： ROS Task Scheduling Task Relevance multi-core system

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ROS Task Scheduling Algorithm in multi-core system

ROS Task Scheduling Algorithm in Multi-Core System

引用

International Conference on Parallel and Distributed systems (ICPADS)

作者： Nan Ding Xianghua Meng Yawen Zhao Di Wu College of Computer Science and Technology Dalian University of Technology Dalian China College of Control Science and Engineering Dalian University of Technology Dalian China

ISBN: (纸本)9781728125848

关键词： ROS Task scheduling Task relevance multi-core system TASK SCHEDULING ROS1 gene Linux multiple system algorithms

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FPGA-Based multi-core Reconfigurable system for SAR Imaging 38

FPGA-Based Multi-core Reconfigurable System for SAR Imaging

引用

38th IEEE International Geoscience and Remote Sensing Symposium (IGARSS)

作者： Di, Wei Chen, Changlin Liu, Yongxiang Natl Univ Def Technol Changsha Hunan Peoples R China

ISBN: (纸本)9781538671504

With the development of the very large scale integration circuit (VLSI), multi-core processors have been developing fast and provide a novel approach to meet the requirements of modern complex computing. Real-time SAR imaging is always a hard problem to deal with since the huge amount of data and complex processing. Therefore, we design a schedulable and scalable multi-core parallel architecture based on FPGA and map the fundamental Chirp Scaling algorithm to the system. The design of the master control core makes the system highly extensible and the dedicated computing cores are designed to accelerate the process. In addition, the system can meet the real-time requirements, and it perfouns well in the resource utilization and the FPGA chip takes up a small space as well.

关键词： SAR imaging multi-core system parallel architecture FPGA

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Real-Time and Energy-Efficient Bearing Fault Diagnosis Using Discriminative Wavelet-Based Fault Features on a multi-core system

Real-Time and Energy-Efficient Bearing Fault Diagnosis Using...

引用

IEEE Intemational Conference on Prognostics and Health Management

作者： Kim, Jaeyoung Kang, Myeongsu Jeong, In-Kyu Jun, Heesung Kim, Jong-Myon Choi, Byeong-Keun Univ Ulsan Sch Elect Elect & Comp Engn Ulsan South Korea Gyeongsang Natl Univ Dept Energy Mech Engn Tongyeong City South Korea

ISBN: (纸本)9781479918942

This paper presents a comprehensive bearing fault diagnosis methodology to prevent unscheduled interruptions in machinery. This method consists of fault signature extraction, discriminative fault feature selection (not only to improve diagnosis but also to reduce computational overhead), and decision making using a k-nearest neighbor classifier. Although the presented method yields very accurate classification, its computational complexity limits its use in real-time applications. To address that issue, this paper introduces a single instruction, multiple data-based multi-core system including 64 low-cost processing elements to support the high computational fault diagnosis method, where the multi-core system is implemented in a Xilinx Virtex-7 field programmable gate array device, operating at 200 MHz clock frequency. In addition, this study compares the performance of the multi-core system with that of high-performance digital signal processors (DSPs) to demonstrate improvement in execution time and energy efficiency. Experimental results using one-second acoustic emission signals sampled at 1 MHz indicate that the multi-core approach achieves 82.5x and 7.9x speedups over Texas Instruments (TI) TMS320C6748 and TMS320C6671, respectively, when executing the same bearing fault diagnosis algorithm. In addition, the presented multi-core approach reduces 21.5x and 4.2x less energy than TMS320C6748 and TMS320C6671, respectively.

关键词： Acoustic emission discrete wavelet packet transform discriminative fault feature selection energy efficiency multi-core system online bearing fault diagnosis

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Q-learning Assisted LASSO-based Thermal Sensor Placement for Thermal-aware multi-core systems

Q-learning Assisted LASSO-based Thermal Sensor Placement for...

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： Chen, Kun-Chih (Jimmy) Wang, Lei-Qi Natl Yang Ming Chiao Tung Univ Inst Elect Hsinchu Taiwan Natl Sun Yat Sen Univ Dept Comp Sci & Engn Kaohsiung Taiwan

ISBN: (纸本)9798350330991;9798350331004

Thermal problems become severe in contemporary multi-core systems because of the complicated workload and high power density. The problems impact the system performance and damage the system reliability. The practical way to monitor the system temperature is to place number-limited thermal sensors on multi-core systems. Unfortunately, finding proper locations for thermal sensor placement is an NP-hard problem. Many pieces of research proposed methods to allocate number-limited thermal sensors under different perspectives. However, the conventional methods still do not consider the time-varying temperature distribution or the correlation between different thermal hotspot points. To solve these problems, we apply the Q-learning method to assist with thermal sensor placements determined by the Least Absolute Shrinkage and Selection Operator (LASSO) theory. While LASSO primarily excels in feature selection, Q-learning is better equipped to handle dynamic environmental changes and interdependencies. Thus, we employ the Q-learning method to formulate a precise cost function for accurately estimating the outcomes following the placement of a thermal sensor at a specific location. Compared with the state-of-the-art, our proposed methods, using both the LASSO-based method and the Q-learning Assisted LASSO method, reduce the average errors by 67%-85% and 69%-87%, respectively, and the maximum errors by 80%-92% and 82%-93%.

关键词： thermal sensor multi-core system LASSO Q-learning sensor placement

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SPAMeR: Speculative Push for Anticipated Message Requests in multi-core systems 51

SPAMeR: Speculative Push for Anticipated Message Requests in...

引用

51st International Conference on Parallel Processing (ICPP)

作者： Wu, Qinzhe Ekanayake, Ashen Li, Ruihao Beard, Jonathan John, Lizy K. Univ Texas Austin Austin TX 78712 USA Arm Inc Austin TX USA

ISBN: (纸本)9781450397339

With increasing core counts and multiple levels of cache memories, scaling multi-threaded and task-level parallel workloads is continuously becoming a challenge. A key challenge to scaling the number of communicating tasks (or threads) is the rate at which existing communication mechanisms scale (in terms of latency and bandwidth). Architectures with hardware accelerated queuing operations have the potential to reduce the latency and improve scalability of moving data between processing elements, reducing synchronization penalties, and thereby improving the performance of task-level parallel workloads. While hardware queues reduce synchronization penalties, they cannot fully hide load-to-use latency, i.e., perfect pipelines often are not realized. There is the potential, however, for better overlap. If the inter-processor communication latency is equal to or less than the time spent processing a message at the consumer, any and all latency may be overlapped while the consumer is processing. We exploit this property to speedup parallel applications above and beyond existing hardware queues. In this paper, we present SPAMeR, a speculation mechanism built on top of a state-of-the-art hardware-driven message queue architecture. SPAMeR has the capability to speculatively push messages in anticipation of consumer message requests. Unlike pre-fetch approaches which predict what addresses to fetch next, with a queue we know exactly what data is needed next but not when it is needed;SPAMeR adds algorithms that attempt to predict this. We evaluate the effectiveness of SPAMeR with a set of diverse task-parallel benchmarks utilizing the gem5 full system simulator, and observe a 1.33x average speedup.

关键词： multi-core system parallel computing message queue speculation

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Algorithmic Approach for Applying Load Balancing During Task Migration in multi-core system 3

Algorithmic Approach for Applying Load Balancing During Task...

引用

International Conference Parallel Distributed Grid Computing

作者： Johari, Suchi Kumar, Arvind Jaypee Univ Informat Technol Dept Comp Sci Waknaghat India

ISBN: (纸本)9781479976836

As day by day multi core systems are increasing researchers are looking for various techniques to reduce power consumption and improve performance. In multi-core processors several cores are placed on the single grid and multiple tasks are distributed over these cores for processing [1]. Each core is responsible for the processing of the task allocated to it. This may lead to problems like load balancing on different cores, as various tasks are allocated to the single core. Now if there is a situation that a single core or a cluster of cores have large number of task to be executed while some of the cores remain free then there is a need of a technique called task migration. Task migration is not similar to load balancing in any aspect. In task migration only the migration of the task from overloaded core to other core is done but till now maintaining load balancing during task migration was an issue[2]. But if the load balancing is done at the time of the task migration then it will improve performance about 99%. This paper emphasis on various algorithms for load balancing during task migration in a multi-core system, so that number of tasks on different cores are distributed fairly. This paper also discusses the algorithms for deciding which task is to be migrated. With the help of these algorithms, performance and response time is improved to a great extent.

关键词： Load Balancing Task Migration multi-core system Deadline Threshold value

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High-Performance Parallel Fault Simulation for multi-core systems 29

High-Performance Parallel Fault Simulation for Multi-Core Sy...

引用

29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)

作者： Karami, Masoomeh Haghbayan, Mohammad-hashem Ebrahimi, Masoumeh Nejatollahi, Hamid Tenhunen, Hannu Plosila, Juha Univ Turku Dept Future Technol Turku Finland KTH Royal Inst Technol Dept Elect & Embedded Syst Kista Sweden Univ Calif Irvine Irvine CA USA

ISBN: (纸本)9781665414555

Fault simulation is a time-consuming process that requires customized methods and techniques to accelerate it. multi-threading and multi-core approaches are two promising techniques that can be exploited to accelerate the fault simulation process by using different parts of the hardware at the same time. However, an efficient parallelization is obtained only by the refinement of software with respect to the hardware platform. In this paper, a parallel multi-thread fault simulation technique is proposed to accelerate the simulation process on multi-core platforms. In this approach, the gate input values are independently assigned to each thread. Each input value carries the information of several parallel simulation processes. This provides a multithread parallel fault simulation environment. The experimental results show that the proposed technique can efficiently use the hardware platform. In a single-core platform. the proposed technique can reduce the time by 25% while in a dual-core increasing the thread approximately halves the execution time.

关键词： multi-core system multi-threading parallelization fault simulation

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SPAMeR: Speculative Push for Anticipated Message Requests in multi-core systems 22

SPAMeR: Speculative Push for Anticipated Message Requests in...

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Proceedings of the 51st International Conference on Parallel Processing

作者： Qinzhe Wu Ashen Ekanayake Ruihao Li Jonathan Beard Lizy John University of Texas at Austin United States of America Arm United States of America

ISBN: (纸本)9781450397339

With increasing core counts and multiple levels of cache memories, scaling multi-threaded and task-level parallel workloads is continuously becoming a challenge. A key challenge to scaling the number of communicating tasks (or threads) is the rate at which existing communication mechanisms scale (in terms of latency and bandwidth). Architectures with hardware accelerated queuing operations have the potential to reduce the latency and improve scalability of moving data between processing elements, reducing synchronization penalties, and thereby improving the performance of task-level parallel workloads. While hardware queues reduce synchronization penalties, they cannot fully hide load-to-use latency, i.e., perfect pipelines often are not realized. There is the potential, however, for better overlap. If the inter-processor communication latency is equal to or less than the time spent processing a message at the consumer, any and all latency may be overlapped while the consumer is processing. We exploit this property to speedup parallel applications above and beyond existing hardware queues. In this paper, we present SPAMeR, a speculation mechanism built on top of a state-of-the-art hardware-driven message queue architecture. SPAMeR has the capability to speculatively push messages in anticipation of consumer message requests. Unlike pre-fetch approaches which predict what addresses to fetch next, with a queue we know exactly what data is needed next but not when it is needed; SPAMeR adds algorithms that attempt to predict this. We evaluate the effectiveness of SPAMeR with a set of diverse task-parallel benchmarks utilizing the gem5 full system simulator, and observe a 1.33 × average speedup.

关键词： parallel computing message queue multi-core system speculation

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