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A shared libraries aware and bank partitioning-based mechanism for multicore architecture

SOFT COMPUTING 2023年第13期27卷 8775-8787页

作者： Yang, Hubin Xu, Shuaixin Chen, Yucong Liu, Gang Zhou, Rui Zhou, Qingguo Li, Kuan-Ching Lanzhou Univ Sch Informat Sci & Engn Lanzhou Gansu Peoples R China Providence Univ Dept Comp Sci & Informat Engn Taichung Taiwan

Dynamic random-access memory (DRAM) consists of several banks, which are shared resources among cores. Memory interference is caused by sharing with banks among cores, which results in overall system performance reduction. This will exacerbate the problem because shared libraries are commonly used in modern operating systems. The physical memories used by shared libraries are often distributed throughout all banks in DRAM, and shared library codes are regularly run. This will result in a large number of row-buffer conflicts and a decrease in system performance. This paper proposes a new shared library awareness and bank partitioning-based mechanism (SBM) that takes into account inter-thread interference caused by shared libraries and assigns allocated DRAM banks to specific cores rather than processes, thus taking advantage of bank-level parallelism (BLP) and improving system performance isolation. We conducted several experiments to assess the degree of performance isolation achieved by SBM. The findings indicate that SBM significantly enhanced performance isolation.

关键词： Isolation Bank partitioning Shared libraries multicore architecture

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Parallelizing Complex Streaming Applications on Distributed Scratchpad Memory multicore architecture

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2014年第6期42卷 875-899页

作者： Chen, Shin-Kai Hung, Cheng-Yu Chen, Ching-Chih Liu, Chih-Wei Natl Chiao Tung Univ Dept Elect Engn Hsinchu Taiwan

multicore processors can provide sufficient computing power and flexibility for complex streaming applications, such as high-definition video processing. For less hardware complexity and power consumption, the distributed scratchpad memory architecture is considered, instead of the cache memory architecture. However, the distributed design poses new challenges to programming. It is difficult to exploit all available capabilities and achieve maximal throughput, due to the combined complexity of inter-processor communication, synchronization, and workload balancing. In this study, we developed an efficient design flow for parallelizing multimedia applications on a distributed scratchpad memory multicore architecture. An application is first partitioned into streaming components and then mapped onto multicore processors. Various hardware-dependent factors and application-specific characteristics are involved in generating efficient task partitions and allocating resources appropriately. To test and verify the proposed design flow, three popular multimedia applications were implemented: a full-HD motion JPEG decoder, an object detector, and a full-HD H.264/AVC decoder. For demonstration purposes, SONY PlayStation3 was selected as the target platform. Simulation results show that, on PS3, the full-HD motion JPEG decoder with the proposed design flow can decode about 108.9 frames per second (fps) in the 1080p format. The object detection application can perform real-time object detection at 2.84 fps at resolution, 11.75 fps at resolution, and 62.52 fps at resolution. The full-HD H.264/AVC decoder applications can achieve nearly 50 fps.

关键词： Parallel programming Streaming application multicore architecture Distributed scratchpad memory architecture

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A Framework for Heuristic Scheduling for Parallel Processing on multicore architecture: A Case Study with Multiview Video Coding

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2009年第11期19卷 1658-1666页

作者： Pang, Yi Sun, Lifeng Wen, Jiangtao (Gene) Zhang, Fengyan Hu, Weidong Feng, Wei Yang, Shiqiang Tsinghua Univ Dept Comp Sci & Technol Beijing 100084 Peoples R China

In this paper, using the Intel multicore architectures and the emerging multiview video coding standard, we introduce a framework for performing analysis, simulation, and evaluation of heuristics scheduling algorithms for implementing computationally intensive algorithms on multicore processors. The framework allows for accurate and quantitative characterization of the performance of dynamic scheduling algorithms for multimedia applications on different multicore processors without actual implementation of the scheduling algorithm and application on the actual platform. Experimental results demonstrate the effectiveness and scalability of our framework.

关键词： Directed acyclic graph multicore architecture scheduling algorithms

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A Highly Unified Reconfigurable multicore architecture to Speedup NTT/INTT for Homomorphic Polynomial Multiplication

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2022年第8期30卷 993-1006页

作者： Su, Yang Yang, Bai-Long Yang, Chen Yang, Ze-Peng Liu, Yi-Wei Rocket Force Univ Engn Sch Operat Support Xian 710025 Peoples R China Engn Univ Peoples Armed Police Sch Cryptog Engn Xian 710086 Peoples R China Xi An Jiao Tong Univ Sch Microelect Xian 710049 Peoples R China

The ring learning with error (RLWE)-based fully homomorphic encryption (FHE) scheme has become one of the most promising FHE schemes. However, its performance is limited by the homomorphic multiplication, especially the polynomial multiplication which occupies major computing resources. Therefore, efficient implementation of polynomial multiplication is crucial for high-performance FHE applications. In this article, we present an area-efficient and highly unified reconfigurable multicore number theoretic transform (NTT)/inverse NTT (INTT) architecture (named MCNA), which employs NTT and INTT for polynomial multiplier with a variable number of reconfigurable processing elements. To reduce latency, MCNA merges the preprocessing and postprocessing into the constant-geometry NTT and INTT, respectively. Also, a reconfigurable modular multiplier based on digital signal processor (DSP) is proposed to speed up the modular multiplication. In order to avoid designing independent memory access pattern for INTT, a unified read/write structure of NTT/INTT is presented. Furthermore, a novel memory access pattern named "cyclic-sharing'' is proposed to reduce 25% memory capacity. MCNA is evaluated on a Xilinx Virtex-7 field-programmable gate array (FPGA) platform. Running at 250-MHz clock frequency, the throughput of MCNA for NTT/INTT achieves 2.78x similar to 9.32x improvements in comparison to prior works, while the area efficiency of lookup table (LUT) and flip-flop (FF) is improved by 1.25x similar to 4.79x. For polynomial multiplication, the throughput of MCNA achieves 3.73x similar to 7.69x enhancements, as well as 1.13x similar to 14.8x area efficiency improvements.

关键词： Constant-geometry (CG) number theoretic transform (NTT)/inverse NTT (INTT) fully homomorphic encryption (FHE) memory access pattern multicore architecture polynomial multiplier reconfigurable processing element (RPE)

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Accelerating prediction of RNA secondary structure using parallelization on multicore architecture

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SADHANA-ACADEMY PROCEEDINGS IN ENGINEERING SCIENCES 2023年第1期49卷 1-5页

作者： Borkar, Pradnya Shinde, Snehal Raghuwanshi, Mukesh Raut, Roshani Symbiosis Int Symbiosis Inst Technol Nagpur Campus Pune 440008 India Indian Inst Informat Technol Nagpur 441108 India Pimpari Chinchwad Coll Engn Pune 411044 India

Due to Covid pandemic, the investigation of bioinformatics, and more specifically the investigation of RNA, has become a major focus of the research. mRNA-based vaccines have been developed by a significant number of academician and scientists. When a virus infects a human body, it first causes disruption to the host's RNA structure, then it transforms the host's RNA into its own genetic structure. As a result, it is vital to research on the process of making predictions about the secondary structures of RNA. The process of predicting the secondary structure of long RNA sequences takes a significant amount of time. This study makes a contribution to the implementation of the algorithm that finds the predicted secondary structure. The methodology for RNA secondary prediction that was employed in this study is based on a dynamic programming model that uses shared memory multicore architecture. The Nearest Neighbor Thermodynamic Model (NNTM) is used as the foundation for the determination of the least amount of free energy. The Gutell database has been used for the RNA sequences of a number of different bacterial species. A comparison was made between the amount of time required to identify the secondary structure of RNA. The length of the RNA sequence is a factor that affects the performance of many existing methods, but the proposed GAfold technique handles sequences of any length. Once the secondary structure has been identified, it helped to detect the virus. It is discovered that the GAfold approach speeds up RNA Secondary structure's prediction. The proposed GAfold algorithm offers a speed increase factor of 2.5 ns on a four-core architecture, 3.09 ns on an eight-core design, and 5.5 ns on a twelve-core architecture. It has been shown that predicting suboptimal structures enhanced the accuracy of the free energy minimization algorithm, which in turn improved the accuracy of full RNA.

关键词： RNA secondary structure prediction parallel algorithm multicore architecture minimum free energy calculation genetic algorithm

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Selective restart of threads for efficient thread-level speculation on multicore architecture

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IEICE ELECTRONICS EXPRESS 2012年第4期9卷 290-295页

作者： Lee, Sungjae Lee, Inhwan Hanyang Univ Sch Elect & Comp Engn Seoul 133791 South Korea

An efficient recovery method for thread-level speculation (TLS) is proposed. The method tracks the inter-thread data dependence as a method for identifying those threads that are obviously unaffected by a data dependence violation. The method is simple to implement. Still, the simulation results using benchmark applications show that the method can significantly reduce the number of unnecessary thread restarts and consequently improve the performance of TLS. Specifically, when compared with the baseline TLS, TLS with the proposed method is 2.3 times faster for IS, 1.7 times faster for equake, and 3.5 times faster for mcf with the use of 64 cores. With the method, the performance of TLS increases steadily up to 64 cores for IS, equake, and mcf, while the speedup of the baseline TLS starts to saturate at 8 or 16 cores.

关键词： multicore architecture thread-level speculation selective restart

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Good programming in transactional memory Game theory meets multicore architecture

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THEORETICAL COMPUTER SCIENCE 2011年第32期412卷 4136-4150页

作者： Eidenbenz, Raphael Wattenhofer, Roger ETH Comp Engn & Networks Lab TIK CH-8092 Zurich Switzerland

In a multicore transactional memory (TM) system, concurrent execution threads interact and interfere with each other through shared memory. The less interference a thread provokes the better for the system. However, as a programmer is primarily interested in optimizing her individual code's performance rather than the system's overall performance, she does not have a natural incentive to provoke as little interference as possible. Hence, a TM system must be designed compatible with good programming incentives (GPI), i.e., writing efficient code for the overall system should coincide with writing code that optimizes an individual thread's performance. We show that with most contention managers (CM) proposed in the literature so far, TM systems are not GPI compatible. We provide a generic framework for CMs that base their decisions on priorities and explain how to modify Timestamp-like CMs so as to feature GPI compatibility. In general, however, priority-based conflict resolution policies are prone to be exploited by selfish programmers. In contrast, a simple non-priority-based manager that resolves conflicts at random is GPI compatible. (C) 2010 Elsevier B.V. All rights reserved.

关键词： Transactional memory Game theory multicore architecture Concurrency Contention management Mechanism design Human factors

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Introducing DOMINO: An Eco-Friendly Asynchronous Hybrid multicore architecture for Green Computing

Introducing DOMINO: An Eco-Friendly Asynchronous Hybrid Mult...

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International Conference on Advances in Big Data, Computing and Data Communication Systems (icABCD)

作者： Mogale, Hope Esiefarienrhe, Michael Gasela, Naison Letlonkane, Lucia North West Univ Dept Comp Sci Mafikeng North West South Africa

ISBN: (纸本)9781538630600

In this paper is we present DOMINO architecture which is a hybrid Asynchronous Asymmetric multicore architecture that is truly Eco-friendliness and is designed for tackling power demanding applications in modern multicore Microprocessors. Our novel design is power efficient using hybrid asynchronous cores that utilize lazy quasi delay-insensitive self timed circuit mechanism. We have further coupled our design with Artificial Intelligence to overcome the problem of dark silicon by incorporating dynamic asymmetric core design. Because of this strategy our hybrid architecture remains power efficient and promotes green computing while powerful enough to enable energy efficient computing for power demanding applications such as deep learning, parallel computing on traditional multicore processors.

关键词： Asynchronous Design multicore architecture Green Computing Harmonious design Parallel architecture And Ecofriendly

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Middleware and multicore architecture: Challenges and Potential Enhancements from Software Engineering Perspective

Middleware and Multicore Architecture: Challenges and Potent...

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IEEE International Conference on Electro Information Technology (EIT)

作者： Alnaeli, Saleh M. Taha, Amanda D. Ali Binder, Sam B. Univ Wisconsin Fox Valley Dept Comp Sci Menasha WI 54952 USA

ISBN: (纸本)9781467399852

An empirical study that examines challenges middleware software systems have to take full advantages of multicore technology is presented. The study is conducted on 9 open source middleware systems containing over 3.39 million lines of code. Each system is analyzed and the inhibitors to parallelization are detected and presented. Additionally, some challenges in analyzing, adapting, and re-engineering middleware systems to better utilize modern multi-core architectures are determined including function side effects. Function side effects categorized based on their types and the complexity they pose in conducting inter-procedural static analysis. The data shows that the most prevalent inhibitor by far is functions called within forloops that have side effects. Moreover, the study shows that parameters by reference and global variables modification are the most prevalent side effects that poses the greatest challenges in reengineering middleware systems to improve their parallelizability to better utilize multi-core architectures. That is, conducting accurate program analysis with existing software engineering tools becomes exigent and impractical with those side effects. The study suggests some software engineering techniques (e.g., refactoring) that have the potential to improve the parallelizability of middleware systems.

关键词： Middleware software engineering multicore architecture parallelization inhibitors function side effects

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Executing Synchronous Dataflow Graphs on a SPM-Based multicore architecture 12

Executing Synchronous Dataflow Graphs on a SPM-Based Multico...

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49th ACM/EDAC/IEEE Design Automation Conference (DAC)

作者： Choi, Junchul Oh, Hyunok Kim, Sungchan Ha, Soonhoi Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul South Korea Hanyang Univ Dept Informat Syst Seoul South Korea Chonbuk Natl Univ Dept Comp Sci & Engn Jeonju South Korea

ISBN: (纸本)9781450311991

In this paper we are concerned about executing synchronous dataflow (SDF) applications on a multicore architecture where a core has a limited size of scratchpad memory (SPM). Unlike traditional multi-processor scheduling of SDF graphs, we consider the SPM size limitation that incurs code and data overlay overhead. Since the scheduling problem is intractable, we propose an EA(evolutionary algorithm)-based technique. To hide memory latency, prefetching is aggressively performed in the proposed technique. The experimental results show that our approach reduces the overlay overhead significantly compared to a non-optimized approach and the previous approach.

关键词： Multiprocessor scheduling synchronous dataflow scratch pad memory multicore architecture memory overlay prefetching

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