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multicore processor computing is not energy proportional: An opportunity for bi-objective optimization for energy and performance

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APPLIED ENERGY 2020年 268卷 114957-114957页

作者： Khokhriakov, Semyon Manumachu, Ravi Reddy Lastovetsky, Alexey Univ Coll Dublin Sch Comp Sci Dublin 4 Ireland

Energy proportionality is the key design goal followed by architects of multicore processors. One of its implications is that optimization of an application for performance will also optimize it for energy. In this work, we show that energy proportionality does not hold true for multicore processors. This finding creates the opportunity for bi-objective optimization of applications for energy and performance. We propose and study a novel application-level bi-objective optimization method for energy and performance for multithreaded dataparallel applications. The method uses two decision variables, the number of identical multithreaded kernels (threadgroups) executing the application and the number of threads per threadgroup, with a given workload partitioned equally between the threadgroups. We experimentally demonstrate the efficiency of the method using four popular and highly optimized multithreaded data-parallel applications, two employing two-dimensional fast Fourier transform and the other two, dense matrix multiplication. The experiments performed on four modern multicore processors show that the optimization for performance alone results in increase in dynamic energy consumption by up to 89% and optimization for dynamic energy alone results in performance degradation by up to 49%. By solving the bi-objective optimization problem, the method determines up to 11 Pareto-optimal solutions. Finally, we propose a qualitative dynamic energy model employing performance events as variables to explain the discovered energy nonproportionality. The model shows that the energy nonproportionality on our experimental platforms for the two data-parallel applications is due to disproportionately energy expensive activity of the data translation lookaside buffer.

关键词： Energy proportionality multicore processor Energy optimization Energy predictive models Bi-objective optimization Fast Fourier transform Matrix multiplication

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multicore processor: Internal structure, architecture, issues, challenges, scheduling strategies and performance 11

Multicore Processor: Internal structure, architecture, issue...

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11th International Conference on Industrial and Information Systems (ICIIS)

作者： Jadon, Shruti Yadav, Rama Shankar Motilal Nehru Natl Inst Technol Dept Comp Sci & Engn Allahabad Uttar Pradesh India

ISBN: (纸本)9781509038183

The challenges of multicore systems in the present scenario are increased demand of high computing and reduced battery power. multicore processing is increasing rapidly as the single core processors are unable to meet the demands of highly advanced time critical applications. The proposed paper discusses the basic internal structure, architectural design, issues and challenges of multicore processor. Further the scheduling techniques for multicore processor and the factors affecting their performance are being discussed in the paper giving a complete understanding of the multicore processors.

关键词： multicore processor structure cache issue co-herency challenges performance scheduling

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Low-Power multicore processor Design With Reconfigurable Same-Instruction Multiple Process

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2014年第6期61卷 423-427页

作者： Yu, Zheng Yu, Zhiyi Yu, Xueqiu Liu, Ningxi Zeng, Xiaoyang Fudan Univ State Key Lab ASIC & Syst Shanghai 201203 Peoples R China

This brief presents a multicore embedded processor with reconfigurable same-instruction multiple process (RSIMP) architecture design to reduce the power consumption of instruction memory (IM), thus reducing the total power of the processor. RSIMP is applied to the scenario in which several cores (each representing a coarse-grained process) execute a highly identical instruction sequence in parallel. They are then reconfigured to master-slave mode in which only the master core fetches instructions and distributes the instructions to the slave core(s), whereas the IM of slave cores are shut down to save power. Experimental results show 13.8% and 21.9% of system power reduction with negligible hardware overhead and performance loss in 2Core and 4Core configurations, respectively, for the benchmarks selected from the long-term evolution (LTE) multiple-input-multiple-output (MIMO) system, the Reed-Solomon (RS) decoder, the H.264/AVC codec, and AES encryption/decryption, compared with the baseline platform.

关键词： Instruction memory (IM) low power multicore processor reconfigurable same-instruction multiple process (RSIMP)

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Performance advantage of reconfigurable cache design on multicore processor systems

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2008年第3期36卷 347-360页

作者： Tao, Jie Kunze, Marcel Nowak, Fabian Buchty, Rainer Karl, Wolfgang Karlsruhe Inst Technol Forschungszentrum Karlsruhe Steinbuch Ctr Comp Karlsruhe Germany Jilin Univ Dept Comp Sci & Technol Changchun 130023 Jilin Peoples R China Univ Karlsruhe Karlsruhe Inst Technol Inst Tech Informat Karlsruhe Germany

With the trends of microprocessor design towards multicore, cache performance becomes more important because an off-chip access would be increasingly expensive due to the competition across the processor cores. A question arises: How to design the cache architecture to prevent a performance bottleneck caused by data accesses? This work studies a reconfigurable cache architecture that can be dynamically configured for meeting the individual demand of running applications. Using a self-developed cache simulator, we first examined how different cache organization and configuration influence the parallel execution of OpenMP applications. The experimental results show that applications benefit from a flexible cache with reconfigurability. This motivated us to go a step further and develop a hardware prototype of this novel architecture.

关键词： cache performance multicore processor simulation reconfigurable architecture

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MP-ORAM: A Novel ORAM Design for multicore processor Systems

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IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING 2024年第4期21卷 3719-3733页

作者： Hussain, Sajid Guo, Hui Li, Tuo Parameswaran, Sri UNSW Sydney Sch Comp Sci & Engn Sydney NSW 2052 Australia MUST Dept Comp Syst Engn Mirpur 10250 Pakistan Univ Sydney Sch Elect & Comp Engn Sydney NSW 2050 Australia Inst Comp Technol CAS State Key Lab Processors Beijing 100190 Peoples R China Zhongguancun Lab Beijing 100081 Peoples R China

Security becomes increasingly critical in today's ubiquitous computing. One vulnerable part of a computing system is the bus between the processor chip and the external off-chip memory, where data transferred on the bus can be snooped. To protect data confidentiality, encryption is commonly used. However, encryption alone is not sufficient since the adversary can still find out useful information using the memory address trace. Oblivious RAM (ORAM) is a strong security measure to prevent such information leak. ORAM hides a true memory access in a round of random (dummy) accesses to the memory such that the data and addresses transferred over the memory buses look oblivious to the adversary. However, the existing ORAM designs often incur a hefty performance overhead, which greatly slows down the processor execution, especially for the multicore processor system where the potentially high memory access frequency from the multiple cores could make the impact of the performance overhead even more critical. To address this issue, we, for the first time, propose to process multiple memory access requests in a single round of dummy memory accesses. As such, we develop a novel ORAM design, called MP-ORAM, that targets the multicore system and is able to simultaneously handle a dynamic number of memory access requests to mitigate the performance overhead without compromising the obliviousness of the off-chip memory access trace. We have built a prototype for MP-ORAM and successfully integrated it into a RISCV-based multicore processor system. The whole system has also been implemented on a Xilinx Ultrascale+ ZCU102 FPGA board, with which we can effectively evaluate the performance of our design. Our evaluation, based on the SPLASH-2 benchmark suit, shows that MP-ORAM improves performance by 51-157% while only consuming up to 22% extra FPGA resources as compared to the baseline design. Furthermore, from the NIST randomness tests on the memory access traces generated by MP-ORA

关键词： Random access memory multicore processing Hardware Process control Field programmable gate arrays Threat modeling Scheduling algorithms ORAM memory data protection secure processor system multicore processor side-channel attacks

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Study on Heat Conduction in a Simulated multicore processor Chip-Part I: Analytical Modeling

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JOURNAL OF ELECTRONIC PACKAGING 2013年第2期135卷 021002-021002-16页

作者： Nakayama, Wataru ThermTech Int Oh Iso Kanagawa 2550004 Japan

A system of temperature calculations is developed to study the conditions leading to hot spot occurrence on multicore processor chips. The analysis is performed on a physical model which incorporates certain salient features of multicore processor. The model has active and background cells laid out in a checkered pattern, and the pattern repeats itself in fine grain active cells. The die has a buried dioxide and a wiring layer stacked on the die body, and heat sources are placed at the wiring layer/buried oxide interface. With this model we explore the effects of various parameters on the target spot temperature. The parameters are the die dimensions, the materials' thermal conductivities, the effective heat transfer coefficients on the die surfaces, the power map, and the spatial resolution with which we view the power and temperature distributions on the die. Closed-form analytical solutions are derived and used to examine the roles of these parameters in creating hot spots. The present paper reports the details of mathematical formulations and steps of temperature calculation. The results for a particular example case are included to illustrate what can be learned from the calculations.

关键词： multicore processor hot spot heat conduction Fourier-series solution checkered pattern cell arrangement

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Complexity of a Problem of Energy Efficient Real-Time Task Scheduling on a multicore processor

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COMPLEXITY 2015年第1期21卷 259-267页

作者： Mishra, Abhishek Tripathi, Anil Kumar Indian Inst Technol Jodhpur Ctr Informat & Commun Technol Jodhpur 342011 Rajasthan India Banaras Hindu Univ Indian Inst Technol Dept Comp Sci & Engn Varanasi 221005 Uttar Pradesh India

The problem of scheduling independent tasks with a common deadline for a multicore processor is investigated. The speed of cores can be varied (from a finite set of core speeds) using software controlled Dynamic Voltage Scaling. The energy consumption is to be minimized. This problem was called the Energy Efficient Task Scheduling Problem (EETSP) in a previous work in which a Monte Carlo algorithm was proposed for solving it. This work investigates the complexity of the EETSP problem. The EETSP problem is proved to be NP-Complete. Under the assumption of P not equal NP, the EETSP problem is also proved to be inapproximable. (C) 2014 Wiley Periodicals, Inc.

关键词： computational complexity dynamic voltage scaling energy efficient scheduling multicore processor inapproximability

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Using Many Small 1T1C Memory Arrays in a Large and Dense multicore processor

Using Many Small 1T1C Memory Arrays in a Large and Dense Mul...

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International Symposium on Memory Systems (MEMSYS)

作者： Carlstedt, Gunnar Rimborg, Mats Chalmers Univ Technol Dept Comp Sci & Engn Gothenburg Sweden

ISBN: (纸本)9781450398008

A memory system for multicore processors with a large number of processing elements (PE) is presented. Each PE has a local memory implemented in one-transistor one-capacitor (1T1C) DRAM technology, and these local memories contain many small memory arrays. The energy consumption and access time are reduced compared to state-of-the-art dynamic memories, while the aggregate bandwidth is increased by orders of magnitude. The memory arrays are composed of 4F(2) cells, with <= 128 bitlines and word-lines. The area overhead for peripheral circuitry is minimized. The word-line driver is a two-transistor demultiplexer, and due to how short the word-lines are, small transistors can be used. The sense amplifiers are multiplexed 4-to-1 for use by several bit-lines. The sense amplifiers are controlled with low voltage current injection to a bus. The address is represented as a combination of eight 1-of-N encoded parts, and their cross products select memory bank, sector, array half, and word-line. The design space is explored by varying the number of banks, sectors, bit-lines and word-lines to find the most ideal combination for a 14 nm technology with 52 nm pitch. Considerable differences in performance measured as area, energy and access time have been found. The optimal constellation provides high area utilization (63 %), low energy consumption (25 fJ/bit) and short access time (515 ps). Finally, a future memory cell at the end of Moore's law is predicted, and its implications for a new emerging computer paradigm, the Surface Based processor (SBP).

关键词： dynamic memory memory system multicore processor sense amplifier word-line driver

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Evaluation of Load Balancing in multicore processor for AnT

Evaluation of Load Balancing in Multicore Processor for <i>A...

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16th International Conference on Network-Based Information Systems (NBiS)

作者： Sakoda, Takeshi Yamauchi, Toshihiro Taniguchi, Hideo Okayama Univ Grad Sch Nat Sci & Technol Okayama 7008530 Japan

ISBN: (纸本)9781479925094;9780769550527

Operating systems (OSes) that is based on microkernel architecture have high adaptability and toughness. In addition, multicore processors have been developed along with the progress of LSI technology. By running a microkernel OS on a multicore processor and distributing the OS server to multiple cores, it is possible to realize load balancing of the OS processing. In this method, transaction processing, which requires a large amount of OS processing, can be provided effectively in a multicore environment. This paper presents evaluations of distributed OS processing performances for various scenarios for AnT operating system that is based on the microkernel architecture in a multicore environment. In these evaluations, we describe the differences in performance by distribution forms when referring the data in a block. Moreover, we use the PostMark and Bonnie benchmark tools to evaluate the effects of load balancing for the distribution forms.

关键词： operating system multicore processor microkernel distributing process

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Efficient Variable Neighborhood Search Performance Based Joint Optimization Task Allocation for multicore processor 2

Efficient Variable Neighborhood Search Performance Based Joi...

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2nd IEEE International Conference on Contemporary Computing and Informatics (IC3I)

作者： Kaur, Prabhjot Agnihotri, Manoj Amritsar Coll Engn & Technol Dept Comp Sci & Engn Amritsar Punjab India

ISBN: (纸本)9781509052561

With an emphasis on energy and thermal issues, the raw computational speed of these processors can only be harnessed with effective scheduling and mapping tools. Software-based schemes for dynamic power and thermal management (DPM and DTM) can be designed to exploit low level control features such as frequency scaling, clock gating, and sleep states to improve the energy consumption and thermal profile of the system. In this paper variable neighborhood search is evaluated for best global optimization solution. The comparison of various parameters has shown best results.

关键词： multicore processor Variable Neighborhood Search Performance Speedup and Makespan

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