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15th IEEE/ACIS International Conference on Computer and Information Science (ICIS)

作者： Hirata, Hiroaki Nunome, Atsushi Shibayama, Kiyoshi Kyoto Inst Technol Fac Informat & Human Sci Sakyo Ku Kyoto 6068585 Japan

ISBN: (纸本)9781509008056

We have been developing a multiprocessor architecture which executes iterations of a loop speculatively in parallel. In this paper, we present speculative memory (SM), in order to enable the large-scale speculation which supports the speculative execution of the iteration of arbitrary size and duration. With SM, a programmer can hint explicitly that iterations of a certain loop are preferable to be executed speculatively in parallel. SM manages multiple values (versions) of speculatively modified data. SM also features the memory renaming and the delayed execution of the program codes, which could be viewed as a dynamic code migration. These can remove the dependencies between loop iterations or alleviate the occurrence of dependency hazards. Thus, SM can improve the success rate of the speculation, and consequently, makes it possible to extract the thread-level parallelism more than ever before.

关键词： thread-level speculation (TLS) speculative multithreading (SpMT) shared-memory multiprocessor parallel architecture multithreaded programming

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Bug Finding Methods for multithreaded Student programming Projects

Bug Finding Methods for Multithreaded Student Programming Pr...

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作者： Naciri, William Malik Virginia Tech | University

The fork-join framework project is one of the more challenging programming assignments in the computer science curriculum at Virginia Tech. Students in Computer Systems must manage a pool of threads to facilitate the shared execution of dynamically created tasks. This project is difficult because students must overcome the challenges of concurrent programming and conform to the project’s specific semantic requirements. When working on the project, many students received inconsistent test results and were left confused when debugging. The suggested debugging tool, Helgrind, is a general-purpose thread error detector. It is limited in its ability to help fix bugs because it lacks knowledge of the specific semantic requirements of the fork-join framework. Thus, there is a need for a special-purpose tool tailored for this project. We implemented Willgrind, a debugging tool that checks the behavior of fork-join frameworks implemented by students through dynamic program analysis. Using the Valgrind framework for instrumentation, checking statements are inserted into the code to detect deadlock, ordering violations, and semantic violations at run-time. Additionally, we extended Willgrind with happens-before based checking in WillgrindPlus. This tool checks for ordering violations that do not manifest themselves in a given execution but could in others. In a user study, we provided the tools to 85 students in the Spring 2017 semester and collected over 2,000 submissions. The results indicate that the tools are effective at identifying bugs and useful for fixing bugs. This research makes multithreaded programming easier for students and demonstrates that special-purpose debugging tools can be beneficial in computer science education.

关键词： Binary Instrumentation multithreaded programming Debugging Thesis

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LB4OMP: A Dynamic Load Balancing Library for multithreaded Applications

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2022年第4期33卷 830-841页

作者： Korndorfer, Jonas H. Muller Eleliemy, Ahmed Mohammed, Ali Ciorba, Florina M. Univ Basel Dept Math & Comp Sci CH-4051 Basel Switzerland HPEs HPC AI EMEA Res Lab ERL Basel Switzerland

Exascale computing systems will exhibit high degrees of hierarchical parallelism, with thousands of computing nodes and hundreds of cores per node. Efficiently exploiting hierarchical parallelism is challenging due to load imbalance that arises at multiple levels. OpenMP is the most widely-used standard for expressing and exploiting the ever-increasing node-level parallelism. The scheduling options in OpenMP are insufficient to address the load imbalance that arises during the execution of multithreaded applications. The limited scheduling options in OpenMP hinder research on novel scheduling techniques which require comparison with others from the literature. This work introduces LB4OMP, an open-source dynamic load balancing library that implements successful scheduling algorithms from the literature. LB4OMP is a research infrastructure designed to spur and support present and future scheduling research, for the benefit of multithreaded applications performance. Through an extensive performance analysis campaign, we assess the effectiveness and demystify the performance of all loop scheduling techniques in the library. We show that, for numerous applications-systems pairs, the scheduling techniques in LB4OMP outperform the scheduling options in OpenMP. Node-level load balancing using LB4OMP leads to reduced cross-node load imbalance and to improved MPI+OpenMP applications performance, which is critical for Exascale computing.

关键词： Dynamic scheduling Processor scheduling Parallel processing Optimal scheduling Libraries Standards Load management Hierarchical parallelism dynamic load balancing self-scheduling runtime library OpenMP multithreaded programming shared-memory systems

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Parallel algorithm development and testing using Petri-object simulation

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INTERNATIONAL JOURNAL OF PARALLEL EMERGENT AND DISTRIBUTED SYSTEMS 2021年第6期36卷 549-564页

作者： Stetsenko, Inna V. Pavlov, Alexander A. Dyfuchyna, Oleksandra Igor Sikorsky Kyiv Polytech Inst Dept Informat & Software Engn Kiev Ukraine

Parallel algorithms are problematic to develop because of the negative influence of synchronisation, complicated behaviour of threads' capturing computing resources. Experimental results show performance time's strong dependence on algorithm parameters, such as the number of subtasks and the complexity of each task. The optimal value of subtask complexity is revealed for the particular algorithm. It is the same for different complexity of the parallelised task (with the same computing resource). To guarantee algorithm speed-up it is important to have a method for investigating the efficiency of parallel algorithm before its implementation on specified computing resources. Stochastic Petri net potentially could be a high accuracy tool for investigating the efficiency of a parallel algorithm. However, a huge number of elements are needed to compose a model of non-trivial algorithm that limits the application of this tool in practice. Petri-object simulation method allows replication of Petri nets with specified parameters and model creation of a list of linked Petri-objects. Basic templates for the model creation of a multithreaded algorithm are developed. Applying these templates, the model of the parallel discrete event simulation algorithm is developed and investigated. By the model results, the algorithm parameters providing the least performance time can be determined.

关键词： multithreaded programming parallel algorithm parallel simulation discrete event simulation stochastic Petri net Java

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An extension for Transactional Memory in OpenMP 21

An extension for Transactional Memory in OpenMP

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25th Brazilian Symposium on programming Languages (SBLP)

作者： Jardim, Andre D. Oliveira, Kevin Cardoso, Diogo J. Di Domenico, Daniel Du Bois, Andre R. Cavalheiro, Gerson G. H. Univ Fed Pelotas Programa Posgrad Comp Pelotas RS Brazil

ISBN: (纸本)9781450390620

The Transactional Memory model was proposed as a mechanism offering a higher-level programming interface to abstract some of the complexities associated with simultaneous access to shared data. Although modern tools for multithreaded programming offer resources, such as programming interface and scheduling facilities, for efficient hardware exploitation, the support for shared data synchronization still reflects classic critical section-based models. This work proposes an extension to the OpenMP, a de facto standard for multithread programming, offering the Transaction Memory model. Different from other approaches found in literature to extend OpenMP with Transaction Memory, we propose an interface that not only promotes the access to a Transaction Memory but also reflects the OpenMP programming style. A specification of the OpenMP extension is presented, and a prototype implementation is evaluated with the help of transactional memory tools in software: the TinySTM library and the TM support offered by the GNU C Compiler (GCC). The proposed interface and its prototype are presented, in the form of an intermediate language, Vanilla-TM, and the interface validation was performed based on the analysis of the results obtained. These results point to the viability of incorporate the proposed extension in an OpenMP dialect, as well as the analysis of the experiments allowed us to conclude that the policies applied for TM management are decisive for a good performance of the programs.

关键词： multithreaded programming Transactional Memory OpenMP

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Multi-threaded Approach to Software High-speed Algorithms for Spectral Analysis of Multi-component Signals 21

Multi-threaded Approach to Software High-speed Algorithms fo...

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21st International Conference on Complex Systems - Control and Modeling Problems (CSCMP)

作者： Yakimov, Vladimir Zaberzhinskij, Borislav Mashkov, Andrey Bukanova, Yuliya Samara State Tech Univ Samara Russia

ISBN: (纸本)9781728167008

The article discusses the development of specialized software measuring-computing system, designed to operational spectral analysis of multicomponent signals based on data processing, obtained by simulating the procedure of binary sign-function quantization. The need to create specialized software measuring-computing system that implements the evaluation of the spectral components of multicomponent processes is caused by the fact that existing proprietary software products either have redundant functionality to solve highly specialized tasks or do not provide the necessary flexibility in the provision, support and modification of libraries that meet specific requirements. The software structure consists of the following main software components: a module for visualization of measurement data, a module for implementing the algorithm for spectral analysis of multicomponent signals, and a data processing converter between the user interface and the module for implementing algorithms. The graphical user interface is implemented using the high-tech integrated development environment Intellij IDEA in the Java 8 multi-platform programming language, which allows extending the functionality of the measurement system. The modules of the metrologically significant part of the software that perform the functions of processing, storing and transmitting measurement data and spectral analysis results are implemented in the resource efficient C ++ 17 language. The use of C ++ provided an opportunity to apply a multi-threaded programming approach in order to improve the performance of the procedures for calculating spectral estimates. Using the mechanism of multithreaded algorithm execution, it became possible to parallelize processor calculations and input-output operations and, as a result, reduce the computational costs of obtaining estimates of the time-frequency characteristics of signals by introducing alternation mechanisms for performing various weakly interconnected subtask

关键词： digital signal processing spectral analysis binary sign-function analog-stochastic quantization software measuring-computing system resource-efficient algorithms multithreaded programming

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Parallelization of a bound-consistency enforcing procedure and its application in solving nonlinear systems

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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2017年 107卷 57-66页

作者： Kubica, Bartlomiej Jacek Warsaw Univ Life Sci Fac Appl Informat & Math Dept Appl Informat Nowoursynowska 159 PL-02776 Warsaw Poland

This paper considers incorporating a bound-consistency enforcing procedure to an interval branch-and-prune method. A heuristic to decide, when to use the developed operator, is proposed. As enforcing the bound-consistency is much more time consuming than performing other narrowing tools, we parallelize the procedure, using Intel TBB. A few parallelization versions are considered. Also, this is a good opportunity to make a case-study of performance of various lock instances, implemented in the TBB package. Numerical results for typical benchmark problems are presented and analyzed. A specific lock version, proper for the application, is proposed. Performance on two architectures is considered: Intel Xeon and Intel Xeon Phi (MIC). (C) 2017 Elsevier Inc. All rights reserved.

关键词： Nonlinear equations systems Interval computations Bound-consistency multithreaded programming TBB Readers-writer lock Big reader lock MIC

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Experimental Performance Comparison of Dynamic Data Race Detection Techniques

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ETRI JOURNAL 2017年第1期39卷 124-134页

作者： Yu, Misun Park, Seung-Min Chun, Ingeol Bae, Doo-Hwan ETRI SW & Content Res Lab Daejeon South Korea Korea Adv Inst Sci & Technol Software Engn Lab Daejeon South Korea

Data races are one of the most difficult types of bugs in concurrent multithreaded systems. It requires significant time and cost to accurately detect bugs in complex largescale programs. Although many race detection techniques have been proposed by various researchers, none of them are effective in all aspects. In this paper, we compare the performance of five recent dynamic race detection techniques: FastTrack, Acculock, Multilock-HB, SimpleLock+, and causally precedes (CP) detection. We experimentally demonstrate the strengths and weaknesses of these dynamic race detection techniques in terms of their detection capability, running time, and runtime overhead using 20 benchmark programs with different characteristics. The comparison results show that the detection capability of CP detection does not differ from that of FastTrack, and that SimpleLock+ generates the lowest overhead among the hybrid detection techniques (Acculock, SimpleLock+, and Multilock-HB) for all benchmark programs. SimpleLock+ is 1.2 times slower than FastTrack on average, but misses one true data race reported from Mutilock-HB on the large-scale benchmark programs.

关键词： Data race Dynamic detection multithreaded programming Debugging happens before Lockset Causally precedes

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A Software Implementation of Speculative Memory 18

A Software Implementation of Speculative Memory

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18th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD)

作者： Fujisawa, Kohei Nunome, Atsushi Shibayama, Kiyoshi Hirata, Hiroaki Kyoto Inst Technol Grad Sch Informat Sci Kyoto Japan Kyoto Inst Technol Fac Informat & Human Sci Kyoto Japan Kyoto Coll Grad Studies Informat Kyoto Japan

ISBN: (纸本)9781509055043

Many techniques for parallelizing a sequentially coded program have been developed and put to practical use, but there are many cases in which program codes cannot be parallelized because it is impossible to assure that their parallel execution does not violate the data dependencies in the program. To parallelize such programs, we have previously proposed speculative memory (SM). With SM, programmers can specify the parallel and speculative execution of threads explicitly in their programs. The SM system manages the memory data that are speculatively read or written by the threads running in parallel. When the system detects inconsistent memory accesses, it recovers the computational state of the program and restarts the execution. If such inconsistencies are not encountered often, we can expect the total execution time of the program to be shorter. In this paper we present a software implementation of SM (SSM). We have developed an SM library by using POSIX threads. In spite of large overheads that are essentially unavoidable in a software implementation, our SSM system can shorten the execution time of a program that compilers cannot parallelize automatically.

关键词： thread-level speculation (TLS) speculative multithreading (SpMT) parallel architecture multithreaded programming

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PARSNIP: Performant Architecture for Race Safety with No Impact on Precision 17

PARSNIP: Performant Architecture for Race Safety with No Imp...

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50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Peng, Yuanfeng Wood, Benjamin P. Devietti, Joseph Univ Penn Philadelphia PA 19104 USA Wellesley Coll Wellesley MA 02181 USA

ISBN: (纸本)9781450349529

Data race detection is a useful dynamic analysis for multithreaded programs that is a key building block in record-and-replay, enforcing strong consistency models, and detecting concurrency bugs. Existing software race detectors are precise but slow, and hardware support for precise data race detection relies on assumptions like type safety that many programs violate in practice. We propose PARSNIP a fully precise hardware-supported data race detector. PARSNIP exploits new insights into the redundancy of race detection metadata to reduce storage overheads. PARSNIP also adopts new race detection metadata encodings that accelerate the common case while preserving soundness and completeness. When bounded hardware resources are exhausted, PARSNIP falls back to a software race detector to preserve correctness. PARSNIP does not assume that target programs are type safe, and is thus suitable for race detection on arbitrary code. Our evaluation of PARSNIP on several PARSEC benchmarks shows that performance overheads range from negligible to 2.6x, with an average overhead of just 1.5x. Moreover, PARSNIP outperforms the state-of-the-art Radish hardware race detector by 4.6x.

关键词： multithreaded programming data race detection hardware support

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