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IEEE International Conference on IC Design and Technology (ICICDT)

作者： Shen, Zixuan Huang, Lei Zhao, Yuansheng Yang, Keyi Wang, Jipeng Liu, Bingqiang Dong, Boyi Wei, Zhengzhe Zheng, Yuanjin Wang, Chao Huazhong Univ Sci & Technol Sch Opt & Elect Informat Wuhan Peoples R China Huazhong Univ Sci & Technol Sch Integrated Circuits Wuhan Peoples R China Nanyang Technol Univ Sch Elect & Elect Engn Singapore Singapore

ISBN: (纸本)9798331517137;9798331517144

In this paper, an energy-efficient low-voltage 7T SRAM-based charge recovery logic NMC macro is proposed. Firstly, a weight-stationary NMC macro architecture in dual clock and voltage domains is proposed to save memory energy consumption at near-threshold regime, without sacrificing computing throughput. Secondly, the charge recovery logic at subthreshold regime is also employed to reduce NMC logic energy consumption, while maintaining the computing speed. Simulation results show that the energy efficiency of the proposed 4Kb 7T-SRAM based CRL NMC macro design is around 3.71 TOPS/W, i.e., 6.49x improvement against the baseline design, when accelerating convolutional operations by 1.8 GOPS at 100 MHz with SRAM operating under 0.6 V and CRL computing under 0.4 V.

关键词： near memory computing charge recovery logic subthreshold operation near-threshold operation SRAM

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Performance Estimation and Prototyping of Reconfigurable near-memory computing Systems 33

Performance Estimation and Prototyping of Reconfigurable Nea...

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33rd International Conference on Field-Programmable Logic and Applications (FPL)

作者： Iskandar, Veronia Abd El Ghany, Mohamed A. Goehringer, Diana Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany German Univ Cairo Dept Elect IES Lab Cairo Egypt Tech Univ Darmstadt Darmstadt Germany Ctr Scalable Data Analyt & Artificial Intelligenc Leipzig Germany

ISBN: (纸本)9798350341515

The concept of near-memory computing (NMC) has emerged as a promising solution to address the memory wall challenges faced by future computing architectures. By utilizing modern systems that integrate 3D-stacked DRAM memory, the NMC paradigm minimizes unnecessary data movement between the memory subsystem and the CPU. FPGA vendors have incorporated 3D-stacked memories into their products to meet the increasing bandwidth requirements of memory-intensive applications, enabling FPGAs to compete with GPU solutions in terms of speed and energy efficiency. Recent NMC proposals focus on different data processing workloads, including graph processing and machine learning. This work addresses the research questions of how to leverage the full bandwidth of 3D-stacked high-bandwidth memory and how to facilitate the adoption of the near-memory computing paradigm.

关键词： High bandwidth memories near memory computing Parallel Architectures Prediction

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Optimizing Behavioral near On-Chip memory computing Systems 33

Optimizing Behavioral Near On-Chip Memory Computing Systems

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33rd International Conference on Application-specific Systems, Architectures and Processors (ASAP)

作者： Si, Qilin Schafer, Benjamin Carrion Univ Texas Dallas Dept Elect & Comp Engn Richardson TX 75083 USA

ISBN: (数字)9781665483087

ISBN: (纸本)9781665483087

This work presents an automated design and optimization flow for near on-chip memory computing systems by placing dedicated hardware accelerators directly next to the on-chip memory. The salient feature of our proposed flow is that it allows the design of these complex systems completely at the behavioral level, thus, allowing a much richer set of optimizations than traditional Register Transfer Level (RTL) based approaches. Moreover, raising the level of design abstraction allows to quickly evaluate the effect of different optimization on the overall area, performance and power. In addition, it allows to quickly generate system with particular area and performance trade-offs by simply setting different synthesis options' combinations. Experimental results setting different constraints show the effectiveness of our proposed approach.

关键词： near memory computing High-Level Synthesis Behavioral SoC design Design Space Exploration

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A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing

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IEEE TRANSACTIONS ON COMPUTERS 2025年第4期74卷 1109-1122页

作者： Li, Zerun Chen, Xiaoming Yang, Yuxin Min, Feng Zhang, Xiaoyu Han, Yinhe Chinese Acad Sci Inst Comp Technol Beijing 100190 Peoples R China Univ Chinese Acad Sci Beijing 100190 Peoples R China

Graph processing plays an important role in many practical applications. However, the inherent characteristics of graph processing, including random memory access and the low computation-to-communication ratio, make it difficult to efficiently execute on traditional computing architectures, such as CPUs and GPUs. near-memory computing has the characteristics of low latency and high bandwidth. It is widely regarded as a promising direction for designing graph processing accelerators. However, the storage space of a single device cannot meet the demand of large-scale graph processing. Using multiple devices will bring lots of inter-device data transmission, which may counteract the benefits of near-memory computing. To fundamentally reduce the data transmission overhead, we propose a data-centric graph processing framework for systems with multiple near-memory computing devices. The framework uses a data-centric programming model as the software hardware interface. For software, we propose an optimized data flow and a heuristic multi-step weighted maximum matching algorithm to achieve efficient inter-device communication and ensure load balancing. For hardware, we design a data reuse driven task controller and a data type-aware on-chip memory, which can effectively improve the utilization of the on-chip memory. Compared with the two most recent near-memory graph accelerators, our framework significantly reduces energy consumption and inter-device communication.

关键词： Bandwidth memory management Computational modeling System-on-chip Software Hardware Computer architecture Three-dimensional displays Performance evaluation Data communication Large-scale graph processing near memory computing memory system accelerator

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Efficient memory Layout for Pre-Alignment Filtering of Long DNA Reads Using Racetrack memory

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2024年第1期23卷 129-132页

作者： Khan, Asif Ali Hameed, Fazal Shahroodi, Taha Jones, Alex K. Castrillon, Jeronimo Tech Univ Dresden D-01069 Dresden Germany Amer Univ Sharjah AUS Sharjah U Arab Emirates Univ Pittsburgh Pittsburgh PA 15261 USA Delft Univ Technol NL-2628 Delft Netherlands

DNA sequence alignment is a fundamental and computationally expensive operation in bioinformatics. Researchers have developed pre-alignment filters that effectively reduce the amount of data consumed by the alignment process by discarding locations that result in a poor match. However, the filtering operation itself is memory-intensive for which the conventional Von-Neumann architectures perform poorly. Therefore, recent designs advocate compute near memory (CNM) accelerators based on stacked DRAM and more exotic memory technologies such as racetrack memories (RTM). However, these designs only support small DNA reads of circa 100 nucleotides, referred to as short reads. This letter proposes a CNM system for handling both long and short reads. It introduces a novel data-placement solution that significantly increases parallelism and reduces overhead. Evaluation results show substantial reductions in execution time ($1.32\times$1.32x) and energy consumption (50%), compared to the state-of-the-art.

关键词： Bioinformatics Genomics Filtering Filtering algorithms Layout DNA Sequential analysis Domain wall memory near memory computing racetrack memory sequence alignment

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GEM: Ultra-Efficient near-memory Reconfigurable Acceleration for Read Mapping by Dividing and Predictive Scattering

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2023年第12期34卷 3059-3072页

作者： Chen, Longlong Zhu, Jianfeng Peng, Guiqiang Liu, Mingxu Wei, Shaojun Liu, Leibo Tsinghua Univ Sch Integrated Circuits Beijing 100084 Peoples R China Beijing Superstring Acad Memory Technol Dept DRAM Beijing 100176 Peoples R China

Read mapping, which maps billions of reads to a reference DNA, poses a significant performance bottleneck in genomic analysis. Current accelerators for read mapping are primarily bounded by the intensive and random memory access to huge datasets. near-data processing (NDP) infrastructures are promising to provide extremely high bandwidth. However, existing frameworks failed to reach this potential due to poor locality and high redundancy. Our idea is to introduce prediction under the insight that candidate mapping positions become predictable when the reference is organized in coarse-grain slices. We present GEM (Genomic memory), an ultra-efficient near-memory accelerator for read mapping. GEM adopts a novel data-centric framework, named dividing-and-predictive-scattering (DPS), which synthesizes information of seed existence to predict the target mapping locations to reduce memory access redundancy. During preparation, DPS divides the reference into coarse-grained slices and creates predictive filters to assess the likelihood of reads belonging to each slice. During mapping, DPS predicts and scatters reads to considerably fewer slices compared than without prediction. By employing small on-chip SRAM-based predictors with high accuracy, DPS minimizes unnecessary DRAM access and data movement from remote memory. In essence, DPS trades pre-seeding predictors for localized access patterns and low redundancy, hence achieving high throughput for data-intensive applications. We implement GEM by integrating coarse-grain reconfigurable architectures (CGRAs) in the logic layer of a 3D-stacked DRAM infrastructure, utilizing the massive banks as slices. GEM leverages CGRAs for their flexibility in supporting various algorithms tailored to different datasets. Bloom filters are leveraged for slice prediction, providing an error rate below 1%. Evaluation results demonstrate that GEM reduces memory requests by 95% and alignments by 87%, achieving a throughput improvement of 15.3 x

关键词： Data-centric computing dividing and scattering genome assembly near memory computing read mapping reconfigurable computing

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A Configurable Architecture for Efficient Sparse FIR Computation in Real-time Radio Frequency Systems

A Configurable Architecture for Efficient Sparse FIR Computa...

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IEEE/MTT-S International Microwave Symposium (IMS)

作者： Seo, Jamin Mukherjee, Mandovi Rahman, Nael Mizanur Tong, Jianming DeLude, Coleman Krishna, Tushar Romberg, Justin Mukhopadhyay, Saibal Georgia Inst Technol Atlanta GA 30332 USA

ISBN: (数字)9781665496131

ISBN: (纸本)9781665496131

A low-latency and high-throughput, configurable architecture for computing sparse Finite Impulse Response in real-time Radio Frequency domain is proposed. The massively parallel architecture uses distributed control in association with near-memory techniques to optimize area and power. It supports configurability in filter tap locations and handling of locally dense taps, making it more adaptable to Radio Frequency environments.

关键词： Sparse Finite Impulse Response near memory computing Real Time Operation Radio Frequency

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Triple-Skipping near-MRAM computing Framework for AIoT Era

Triple-Skipping Near-MRAM Computing Framework for AIoT Era

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25th Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Chen, Juntong Cai, Hao Liu, Bo Yang, Jun Southeast Univ Natl ASIC Syst Engn Res Ctr Nanjing Peoples R China

ISBN: (纸本)9783981926361

near memory computing (NMC) paradigm shows great significance in non-von Neumann architecture to reduce data movement. The normally-off and instance-on characteristics of spin-transfer torque magnetic random access memory (STT-MRAM) promise energy-efficient storage in the AIoT era. To avoid unnecessary memory-related processing, we propose a novel write-read-calculation triple-skipping (TS) NMC for multiply-accumulate (MAC) operation with minimally modified peripheral circuits. The proposed TS-NMC is evaluated with a custom micro control unit (MCU) in 28-nm high-K metal gate (HKMG) CMOS process and foundry announced universal two-transistor two-magnetic tunnel junction (2T-2MTJ) MRAM cell. The framework consists of a sparse flag which is defined in extra STT-MRAM columns with only 0.73% area overhead, and a calculation block for NMC logic with 9.9% overhead. The TS-NMC can successfully work at 0.6-V supply voltage under 20MHz. This near-MRAM framework can offer up to similar to 95.6% energy saving compared to commercial SRAM refer to ultra-low-power benchmark (ULP-Benchmark). Classification task on MNIST takes 13nJ/pattern. The energy access of memory, calculation, and the total can be reduced by 52.49x, 2.7x, and 11.3x respectively from the TS scheme.

关键词： STT-MRAM near memory computing neural network MAC triple-skipping AIoT

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Triple-skipping near-MRAM computing framework for AIoT era 22

Triple-skipping near-MRAM computing framework for AIoT era

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Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe

作者： Juntong Chen Hao Cai Bo Liu Jun Yang Southeast University Nanjing China

ISBN: (纸本)9783981926361

near memory computing (NMC) paradigm shows great significance in non-von Neumann architecture to reduce data movement. The normally-off and instance-on characteristics of spin-transfer torque magnetic random access memory (STT-MRAM) promise energy-efficient storage in the AIoT era. To avoid unnecessary memory-related processing, we propose a novel write-read-calculation triple-skipping (TS) NMC for multiply-accumulate (MAC) operation with minimally modified peripheral circuits. The proposed TS-NMC is evaluated with a custom micro control unit (MCU) in 28-nm high-K metal gate (HKMG) CMOS process and foundry announced universal two-transistor two-magnetic tunnel junction (2T-2MTJ) MRAM cell. The framework consists of a sparse flag which is defined in extra STT-MRAM columns with only 0.73% area overhead, and a calculation block for NMC logic with 9.9% overhead. The TS-NMC can successfully work at 0.6-V supply voltage under 20MHz. This near-MRAM framework can offer up to ~95.6% energy saving compared to commercial SRAM refer to ultra-low-power benchmark (ULP-Benchmark). Classification task on MNIST takes 13nJ/pattern. The energy access of memory, calculation, and the total can be reduced by 52.49×, 2.7×, and 11.3× respectively from the TS scheme.

关键词： neural network STT-MRAM near memory computing triple-skipping MAC AIoT

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TDPRO: Ultra-low Power ECG Processor with High-Precision Time-Domain computing Engine

TDPRO: Ultra-low Power ECG Processor with High-Precision Tim...

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IEEE International Symposium on Circuits and Systems

作者： Liang Chang Siqi Yang Huinan Wang Jianbo Xiao Xin Zhao Shuisheng Lin Jun Zhou Universiy of Eecronic Science nd Technoogy of Chin Chengdu ChinUniversiy of Eecronic Science nd Technoogy of Chin Chengdu ChinUniversiy of Eecronic Science nd Technoogy of Chin Chengdu ChinUniversiy of Eecronic Science nd Technoogy of Chin Chengdu ChinUniversiy of Eecronic Science nd Technoogy of Chin Chengdu ChinUniversiy of Eecronic Science nd Technoogy of Chin Chengdu ChinUniversiy of Eecronic Science nd Technoogy of Chin Chengdu Chin

ISBN: (数字)9781665484855

ISBN: (纸本)9781665484862

In wearable biomedical signal detection, the low-power consumption is a critical requirement. However, the process of biomedical signal detection with traditional neural-network processor is uneconomical for large data movements. A typical solution is the near memory computing (NMC) method, locating more data near the computing engine to save energy, where the detecting accuracy and power consumption is difficult to be optimized simultaneously. In addition, a suitable computing engine is needed to match both power and computation budget. In this work, we combine the NMC-based ECG processor equipped with a high-precision time-domain engine to perform the detection of arrhythmia, namely TDPRO. The proposed TDPRO supports high precision multiplication and addition operation with 8-bit input and weight parameters. Also, we propose TD-zero-jumping and idle-shutdown technique to further reduce 63% 91% power consumption of the time-domain engine. The error rate of 8-bit MAC operation in the TDPRO is 1.18%, which is suitable for the ECG detection.

关键词： Time Domain near memory computing ECG detection Low power Processor

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