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14th IEEE Asian Solid-State Circuits Conference (A-SSCC)

作者： Tsurumi, Kota Suzuki, Kenta Takeuchi, Ken Chuo Univ Dept Elect Elect & Comnun Tokyo Japan

ISBN: (纸本)9781538664131

This paper proposes Pulse Width Modulation Neuromorphic (PWMNM) circuits, best suitable for near-data computing with SSD. The concept of neuromorphic computing is mimicking human brain with a number of mimicked-neurons of analog circuits. A mimicked-neuron in proposed PWMNM consists of 10 pairs of oscillators & clock counters, a micro controller and a charge pump. Proposed PWMNM achieves high energy efficiency of 6.8TOPS/W (Tera operations per second per Watt) and low power consumption of 1.5 mu W, thanks to matrix product operations are processed with number of output pulses as a function of the time instead of conventional current or voltage operation. Both proposed PWMNM and peripheral circuits of NAND flash memory are fabricated with a 180nm standard CMOS process and PWMNM can be embedded in SSD. Character recognition system is demonstrated by using proposed PWMNM, and the recognition accuracy of 93.3% is achieved.

关键词： Neuromorphic Pulse width modulation Oscillator Charge pump Low power consumption near-data computing

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Affinity Alloc: Taming Not-So near-data computing 23

Affinity Alloc: Taming Not-So Near-Data Computing

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56th IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Wang, Zhengrong Liu, Christopher Beckmann, Nathan Nowatzki, Tony UCLA Los Angeles CA 90024 USA CMU Pittsburgh PA USA

ISBN: (纸本)9798400703294

To mitigate the data movement bottleneck on large multicore systems, the near-data computing paradigm (NDC) offloads computation to where the data resides on-chip. The benefit of NDC heavily depends on spatial affinity, where all relevant data are in the same location, e.g. same cache bank. However, existing NDC works lack a general and systematic solution: they either ignore the problem and abort NDC when there is no spatial affinity, or rely on error-prone manual data placement. Our insight is that the essential affinity relationship, i.e. data A should be close to data B, is orthogonal to microarchitecture details and input sizes. By co-optimizing the data structure and capturing this general affinity information in the data allocation interface, the allocator can automatically optimize for data affinity and load balance to make NDC computations truly near data. With this insight, we propose affinity alloc, a general framework to optimize data layout for near-data computing. It comprises an extended allocator runtime, co-optimized data structures, and lightweight extensions to the OS and microarchitecture. Evaluated on parallel workloads across broad domains, affinity alloc achieves 2.26x speedup and 1.76x energy efficiency over a state-of-the-art near-data computing technique with 72% traffic reduction.

关键词： near-data computing data Layout data Placement data Structure Co-Design Memory Allocation

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General, Flexible and Unified near-data computing

General, Flexible and Unified Near-Data Computing

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作者： Wang, Zhengrong University of California Los Angeles

学位级别：Ph.D., Doctor of Philosophy

Over the past decades, the memory hierarchy has increasingly become the bottleneck in general-purpose processors due to a widening gap between the growing demand for large data and the much slower scaling of conventional memory hierarchies. Therefore, conventional in-core computing suffers from increasingly expensive overheads such as excessive request messages, unnecessary data movement and coherence traffic, as well as limited off-chip band-width, to bring the data from memory to computing cores. To continue the performance and energy efficiency scaling, architects propose near-data computing (NDC) in which computations are offloaded to where the data is. However, existing NDC techniques fall short of providing generality and flexibility across different application domains, programming paradigms, computing substrates, which are crucial to the wide adoption of *** key insight is that the critical missing cornerstone for general and flexible near-data computing is a novel rich-semantic memory abstraction. Unlike existing byte-grained load/store operations, the new interface should express a wide range of rich semantics such as the access pattern, reuse distance, near-data computations, etc. Such high-level information is essential for the system to promptly recognize the program’s long-term behavior and adjust accordingly to reach optimal states. More importantly, the new interface should be as transparent as possible to programmers with automatic compiler analysis and runtime library support. Based on this, we can fundamentally revolutionize the memory interface and co-optimize computation and data *** dissertation explores a new ISA interface - streams - to precisely capture the program’s long-term memory and compute activities. Streams are incorporated into the program’s functional semantics and are exposed to the entire system stack to guide various policies. Our evaluation and analysis suggest serval key findings. First, a set of useful and preva

关键词： Cache optimization In-memory computing Memory hierarchy near-data computing Streams

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Blurring the Lines between Memory and Computation

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IEEE MICRO 2017年第6期37卷 13-15页

作者： Das, Reetuparna Univ Michigan Elect Engn & Comp Sci Dept Ann Arbor MI 48109 USA

Traditionally, researchers have attempted to address the memory wall by building a deep memory hierarchy. Another solution is to move computation closer to memory, which is often referred to as processing in memory (PIM). Past PIM solutions tried to move computing logic near memory by integrating DRAM with a logic die using 3D stacking. This helps reduce data movement energy and increase bandwidth; however, the functionality and design of memory itself remains unchanged. An even more exciting technology is one that dissolves the line that distinguishes memory from computational units. nearly three-fourths of silicon in processor and main memory dies is simply to store and access data. Harnessing this silicon area by repurposing it to perform computation can lead to massively parallel computational processing. Furthermore, we naturally save the vast amounts of energy spent in shuffling data back and forth between computational and storage units, and memory bandwidth becomes a meaningless metric. [ABSTRACT FROM AUTHOR]

关键词： accelerators cache energy efficiency memory near-data computing

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Kobold: Simplified Cache Coherence for Cache-Attached Accelerators

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2023年第1期22卷 41-44页

作者： Brana, Jennifer Schwedock, Brian C. C. Manerkar, Yatin A. A. Beckmann, Nathan Univ Portland Pittsburgh PA 15213 USA Carnegie Mellon Univ Pittsburgh PA 15213 USA Univ Michigan Ann Arbor MI 48104 USA

The ever-increasing cost of data movement in computer systems is driving a new era of data-centric computing. One of the most common data-centric paradigms is near-data computing (NDC), where accelerators are placed inside the memory hierarchy to avoid the costly transfer of data to the core. NDC systems show immense potential to improve performance and energy efficiency. Unfortunately, adding accelerators into the memory hierarchy incurs significant complexity for system integration because accelerators often require cache-coherent access to memory. The complex coherence protocols required to handle both cores and cache-attached accelerators result in significantly higher verification costs as well as an increase in directory state and on-chip network traffic. Furthermore, these mechanisms can cause cache pollution and worsen baseline processor performance. To simplify the integration of cache-attached accelerators, we present Kobold, a new coherence protocol and implementation which restricts the added complexity of an accelerator to its local tile. Kobold introduces a new directory structure within the L2 cache to track the accelerator's private cache and maintain coherence between the core and accelerator. A minor modification to the LLC protocol also enables accelerators to improve performance by bypassing the local L2. We verified Kobold's stable-state coherence protocols using the Murphi model checker and estimated area overhead using Cacti 7. Kobold simplifies integration of cache-attached accelerators, adds only 0.09% area over the baseline caches, and provides clear performance advantages versus naive extensions of existing directory coherence protocols.

关键词： Coherence Protocols Engines Complexity theory Multicore processing Costs Memory management Cache coherence data-centric near-data computing

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data Movement Aware Computation Partitioning 17

Data Movement Aware Computation Partitioning

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50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Tang, Xulong Kislal, Orhan Kandemir, Mahmut Karakoy, Mustafa Penn State Univ University Pk PA 16802 USA TOBB Univ Econ & Technol Ankara Turkey

ISBN: (纸本)9781450349529

data access costs dominate the execution times of most parallel applications and they are expected to be even more important in the future. To address this, recent research has focused on near data Processing (NDP) as a new paradigm that tries to bring computation to data, instead of bringing data to computation (which is the norm in conventional computing). This paper explores the potential of compiler support in exploiting NDP in the context of emerging manycore systems. To that end, we propose a novel compiler algorithm that partitions the computations in a given loop nest into subcomputations and schedules the resulting subcomputations on different cores with the goal of reducing the distance-to-data on the on-chip network. An important characteristic of our approach is that it exploits NDP while taking advantage of data locality. Our experiments with 12 multithreaded applications running on a state-of-the-art commercial manycore system indicate that the proposed compiler-based approach significantly reduces data movements on the on-chip network by taking advantage of NDP, and these benefits lead to an average execution time improvement of 18.4%.

关键词： Multicore Architectures near-data computing Compiler

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near-Stream computing: General and Transparent near-Cache Acceleration 28

Near-Stream Computing: General and Transparent Near-Cache Ac...

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28th Annual IEEE International Symposium on High-Performance Computer Architecture (HPCA)

作者： Wang, Zhengrong Weng, Jian Liu, Sihao Nowatzki, Tony Univ Calif Los Angeles Los Angeles CA 90095 USA

ISBN: (纸本)9781665420273

data movement and communication have become the primary bottlenecks in large multicore systems. The near-data computing paradigm provides a solution: move computation to where the data resides on-chip. Two challenges keep near-data computing from the mainstream: lack of programmer transparency and applicability. Programmer transparency requires providing sequential memory semantics with distributed computation, which requires burdensome coordination. Broad applicability requires support for combinations of address patterns (e.g. affine, indirect, multi-operand) and computation types (loads, stores, reductions, atomics). We find that streams - coarse grain memory access patterns - are a powerful ISA abstraction for near data offloading. Tracking data access at stream-granularity heavily reduces the burden of coordination for providing sequential semantics. Decomposing the problem using streams means that arbitrary combinations of address and computation patterns can be combined for broad generality. With this insight, we develop a paradigm called near-stream computing, comprising a compiler, CPU ISA extension, and a microarchitecture that facilitate programmer transparent computation offloading to shared caches. We evaluate our system on OpenMP kernels that stress broad addressing and compute behavior, and find that 46% of dynamic instructions can be offloaded to remote banks, reducing the network traffic by 76%. Overall it achieves 2.13x speedup over a state-of-the-art near-data computing technique, with a 1.90x energy efficiency gain.

关键词： Stream-Based ISAs Programmer-Transparent Acceleration near-data computing

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Orchestrating near-data FPGA Accelerators using Unix Pipes 7

Orchestrating Near-Data FPGA Accelerators using Unix Pipes

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7th International Symposium on computing and Networking (CANDAR)

作者： Schmid, Robert Plauth, Max Wenzel, Lukas Eberhardt, Felix Polze, Andreas Univ Potsdam Hasso Plattner Inst Digital Engn Operating Syst & Middleware Grp Potsdam Germany

ISBN: (纸本)9781728152684

near-data accelerators play an important role in satisfying the ever growing demand for compute resources. However, for an efficient integration of near-data computing resources into applications, a flexible programming model and suitable abstractions on the operating system level are required. This paper presents Metal FS, a framework that enables users and applications to orchestrate computations on a NVMe+FPGA near-data computing device through standard shell syntax, including the pipe operator. A user-space NVMe file system interface exposes the storage resources of the NVMe+FPGA accelerator. Computation pipelines expressed on the shell are mapped to pre-defined functional elements of a coarse-grained FPGA overlay, enabling data transformations to be performed in proximity to the data source. Overall, Metal FS greatly increases developer productivity for applications targeting near-data computing accelerators.

关键词： near-data computing FPGA Programming Model

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A Virtual File System for On-Demand Processing of Multidimensional datasets 16

A Virtual File System for On-Demand Processing of Multidimen...

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Conference on Diversity, Big data, and Science at Scale (XSEDE)

作者： Wetzel, Arthur Bakal, Jennifer Dittrich, Markus Carnegie Mellon Univ Pittsburgh Supercomp Ctr Pittsburgh PA 15213 USA BioTeam Inc Middleton MA 01949 USA

ISBN: (纸本)9781450347556

Diverse areas of science and engineering are increasingly driven by high-throughput automated data capture and analysis. Modern acquisition technologies, used in many scientific applications (e.g., astronomy, physics, materials science, geology, biology, and engineering) and often running at gigabyte per second data rates, quickly generate terabyte to petabyte datasets that must be stored, shared, processed and analyzed at similar rates. The largest datasets are often multidimensional, such as volumetric and time series data derived from various types of image capture. Costeffective and timely processing of these data require system and software architectures that incorporate on-the-fly processing to minimize I/O traffic and avoid latency limitations. In this paper we present the Virtual Volume File System, a new approach to on-demand processing with file system semantics, combining these principles into a versatile and powerful data pipeline for dealing with some of the largest 3D volumetric datasets. We give an example of how we have started to use this approach in our work with massive electron microscopy image stacks. We end with a short discussion of current and future challenges.

关键词： active storage file system multidimensional data processing near-data computing data sharing data duplication hierarchical data storage

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AQUOMAN: An Analytic-Query Offloading Machine 53

AQUOMAN: An Analytic-Query Offloading Machine

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53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Xu, Shuotao Bourgeat, Thomas Huang, Tianhao Kim, Hojun Lee, Sungjin Arvind MIT CSAIL Cambridge MA 02139 USA DGIST Daegu South Korea

ISBN: (纸本)9781728173832

Analytic workloads on terabyte data-sets are often run in the cloud, where application and storage servers are separate and connected via network. In order to saturate the storage bandwidth and to hide the long storage latency, such a solution requires an expensive server cluster with sufficient aggregate DRAM capacity and hardware threads. An alternative solution is to push the query computation into storage servers. In this paper we present an in-storage Analytics QUery Offloading MAchiNe (AQUOMAN) to "offload" most SQL operators, including multi-way joins, to SSDs. AQUOMAN executes Table Tasks, which apply a static dataflow graph of SQL operators to relational tables to produce an output table. Table Tasks use a streaming computation model, which allows AQUOMAN to process queries with a reasonable amount of DRAM for intermediate results. AQUOMAN is a general analytic query processor, which can be integrated in the database software stack transparently. We have built a prototype of AQUOMAN in FPGAs, and using TPC-H benchmarks on 1TB data sets, shown that a single instance of 1TB AQUOMAN disk, on average, can free up 70% CPU cycles and reduce DRAM usage by 60%. One way to visualize this saving is to think that if we run queries sequentially and ignore inter-query page cache reuse, MonetDB running on a 4-core, 16GB-DRAM machine with AQUOMAN augmented SSDs performs, on average, as well as a MonetDB running on a 32-core, 128GB-DRAM machine with standard SSDs.

关键词： Accelerator SQL analytics near-data computing FPGA Flash storage database

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